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参数资料
型号： LB11872H
厂商： SANYO SEMICONDUCTOR CO LTD
元件分类： 运动控制电子
英文描述： BRUSHLESS DC MOTOR CONTROLLER, 1.2 A, PDSO30
封装： HSOP-28/30
文件页数： 4/11页
文件大小： 125K
代理商： LB11872H
LB11872H
No.7257-2/11
Allowable Operating Conditions at Ta = 25
°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
10 to 28
V
6.3 V regulator-voltage output current
IREG
0 to -20
mA
LD pin applied voltage
VLD
0 to 28
V
LD pin output current
ILD
0 to 15
mA
FGS pin applied voltage
VFG
0 to 28
V
FGS pin output current
IFG
0 to 10
mA
Electrical Characteristics at Ta
= 25°C, VCC = VM = 24V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply current 1
ICC1
Stop mode
5
7
mA
Supply current 2
ICC2
Start mode
17
22
mA
Output saturation voltages VAGC = 3.5V
SOURCE (1)
VSAT1-1
IO = 0.5A, RF = 0Ω
1.7
2.2
V
SOURCE (2)
VSAT1-2
IO = 1.0A, RF = 0Ω
2.0
2.7
V
SINK (1)
VSAT2-1
IO = 0.5A, RF = 0Ω
0.4
0.9
V
SINK (2)
VSAT2-2
IO = 1.0A, RF = 0Ω
1.0
1.7
V
Output leakage current
IO (LEAK)
VCC = 28V
100
μA
6.3V Regulator-voltage output
Output voltage
VREG
5.90
6.25
6.60
V
Voltage regulation
ΔVREG1
VCC = 9.5 to 28V
50
100
mV
Load regulation
ΔVREG2
Iload = -5 to -20mA
10
60
mV
Temperature coefficient
ΔVREG3
Design target value*1
0
mV/
°C
Hall amplifier block
Input bias current
IB (HA)
Differential input : 50mVp-p
2
10
μA
Differential input voltage range
VHIN
SIN wave input
50
*600
mVp-p
Common-phase input voltage range
VICM
Differential input : 50mVp-p
2.0
VCC-2.5
V
Input offset voltage
VIOH
Design target value*1
-20
20
mV
FG amplifier and schmitt block (IN1)
Input amplifier gain
GFG
5
Times
Input hysteresis (high to low)
VSHL
0
mV
Input hysteresis (low to high)
VSLH
-10
mV
Hysteresis width
VFGL
Input conversion
4
7
12
mV
Low-voltage protection circuit
Operating voltage
VSD
8.4
8.8
9.2
V
Hysteresis width
ΔVSD
0.2
0.4
0.6
V
Thermal protection circuit
Thermal shutdown operating
temperature
TSD
Design target value*1 (junction temperature)
150
180
°C
Hysteresis width
ΔTSD
Design target value*1 (junction temperature)
40
°C
Current limiter operation
Acceleration limit voltage
VRF1
0.53
0.59
0.65
V
Deceleration limit voltage
VRF2
0.32
0.37
0.42
V
Error amplifier
Input offset voltage
VIO (ER)
Design target value*1
-10
10
mV
Input bias current
IB (ER)
-1
1
μA
High-level output voltage
VOH (ER)
IOH = -500μA
VREG-1.2
VREG-0.9
V
Low-level output voltage
VOL (ER)
IOL = 500μA
0.9
1.2
V
DC bias level
VB (ER)
-5%
1/2VREG
5%
V
Note* : Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input. amplitudes should be held to under 350mVp-p.
*1 : This parameter is a design target value and is not measured.
Continued on next page.
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