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参数资料
| 型号： | LB1870M |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 1 A, PDSO36 |
| 封装： | MFP-36 |
| 文件页数： | 7/11页 |
| 文件大小： | 108K |
| 代理商： | LB1870M |
Pin Functions
Equivalent Circuit Block Diagram
No. 4356-5/11
LB1870, 1870M
Symbol
Function
Notes
IN1 to 3+,
Hall element input
Taken as high when IN+ > IN–, and as low otherwise.
IN1 to 3–
OUT1 to 3
Outputs
Capacitors are inserted between these pins and ground.
GND1
Sub-ground
Output block ground. Connect to GND2.
GND2
Ground
Ground for circuits other than the output block.
Rf
Output current detection
Connect a small resistor between this pin and ground.
Set the maximum output current so that I OUT = 0.58/Rf.
VCC
Power supply
VREG
Power supply stabilization output
Connect a capacitor between this pin and GND2.
Internal circuit power supply stabilization.
OSC
Crystal oscillator
8 MHz max
E. CLK
External clock
7 kHz max
FC
Control amplifier frequency correction
Connect a capacitor between this pin and GND2.
EI
Error amplifier input
EO
Error amplifier output
LD
Phase lock detector output
On when the PLL phase is locked. This pin is an open collector output.
PD
Phase comparator output
PLL phase comparator output
N1, N2
Divisor switching
S/S
Start/stop
Start on low.
Stop on high or open.
FGS
FG pulse output
Pulse output following the FG Schmitt comparator.
This pin is an open-collector output.
FG OUT
FG amplifier output
A minimum amplitude of 400 mVp-p is required.
FG IN–
FG amplifier input
AGC
AGC amplifier frequency characteristics correction
Connect a capacitor between this pin and GND2.
OSC
N1
N2
EI
EO
FC
VCC
U
V
W
Rf
GND1
LD
PD
+
--
+
--
+
--
S / S
AGC
Vreg
(6.3V)
FG IN--
FG OUT
FGS OUT
EXT.
CLK
GND2
OCL
LVSD
TSD
EXT
CLK
PLL
Divider and
switching circuit
Lock detection
circuit
Hall amplifier matrix
AGC
circuit
Regu-
lator
V-type
control
Output
control
circuit
Output
circuit
Inte-
grating
amplifier
FG
ampli-
fier
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