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参数资料
| 型号： | LB1881M |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 1 A, PDSO30 |
| 封装： | MFP-30 |
| 文件页数： | 2/6页 |
| 文件大小： | 216K |
| 代理商： | LB1881M |
No. 4455-2/6
LB1881M
Electrical Characteristics at Ta = 25°C, VCC1 = 5 V, VCC2 = 7 V, VS = 3 V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
ICC1VBR = 5 V
3.0
5.0
mA
Supply current
ICC2VBR = 5 V
6.5
10.0
mA
IS
VBR = 5 V, RL = ∞
5.0
mA
Output quiescent current
ICCOQ
VSTBY = 0 V
100
A
ISOQ
VSTBY = 0 V, RL = ∞
150
A
Output saturation voltage
VO(sat)
IOUT = 0.6 A, sink + source
1.7
V
Output TRS withstand voltage
VO(sus)
IOUT = 20 mA*112
V
Output quiescent voltage
VOQ
VBR = 5 V
1.45
1.55
1.65
V
Hall amplifier input offset voltage
VHOFFSET
*1–5
+5
mV
Hall amplifier common mode input
VHCOM
1.4
2.8
V
voltage range
Hall I/O voltage gain
GVHO
Rangle = 8.2 k
34.0
37.0
40.0
dB
Brake pin high level voltage
VBRH
2.0
V
Brake pin low level voltage
VBRL
0.8
V
Brake pin input current
IBRIN
120
A
Brake pin leakage current
IBRLEAK
–30
A
FRC pin high level voltage
VFRCH
2.8
V
FRC pin low level voltage
VFRCL
1.2
V
FRC pin input current
IFRCIN
100
A
FRC pin leakage current
IFRCLEAK
–30
A
Upper side residual voltage
VXH
IOUT = 100 mA, VCC2 = 6 V, VS = 2 V
0.285
0.455
V
Lower side residual voltage
VXL
IOUT = 100 mA, VCC2 = 6 V, VS = 2 V
0.350
0.440
V
Residual voltage inflection point
VSVX
IOUT = 100 mA, VCC2 = 6 V*1
0.9
V
Overlap level
OL
VCC2 = 6 V, VS = 3 V, RL = 100 (Y)
60
70
80
%
Overlap vertical difference
OL
VCC2 = 6 V, VS = 3 V, RL = 100 (Y)
–10
0
+10
%
Standby on voltage
VSTBYL
*2
–0.2
+0.8
V
Standby off voltage
VSTBYH
25
V
Standby pin bias current
ISTBYIN
100
A
Thermal protection circuit operating
TTSD
*1
150
180
210
°C
temperature
Thermal protection circuit hysteresis
TTSD
*115
°C
FG amplifier input offset voltage
VFG OFFSET
–8
+8
mV
Open loop voltage gain
GVFG
f = 10 kHz
43
dB
Source output saturation voltage
VFG OU
IO = –2 mA
3.7
V
Sink output saturation voltage
VFG OD
IO = 2 mA
1.3
V
Common mode signal exclusion ratio
GHR
*180
dB
FG amplifier common mode input
VFG CH
0
3.5
V
voltage range
Phase margin
φM
*120
deg
Schmitt amplifier threshold voltage
VFGS SH
VFGIN+ = 2.5 V,
2.45
2.50
2.55
V
when VFGOUT2 goes from high to low
Schmitt amplifier hysteresis width
VFGS HIS
VFGIN+ = 2.5 V
20
40
60
mV
Note: 1. These are target settings, and are not measured. The overlap ratings are taken as test ratings without change.
2. When the standby pin is open the IC will be in the standby state.
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