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参数资料
| 型号： | LB1922 |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 3.1 A, PDIP28 |
| 封装： | HEAT SINK, SDIP-28 |
| 文件页数： | 6/10页 |
| 文件大小： | 101K |
| 代理商： | LB1922 |
LB1922 Functional Description and Notes on External Components
1. Speed control circuit
Speed control in this IC is implemented with the combination of a speed discriminator circuit and a PLL circuit. The
speed discriminator circuit outputs an error output once every two FG periods using a charge pump technique. The
PLL circuit outputs a phase error once every FG period, also using a charge pump technique. As compared to the
earlier technique of only using a speed discriminator circuit, the combination of a speed discriminator circuit and a
PLL circuit is better able to suppress speed fluctuations when used in situations where large load variations are
applied to the motor. Since the FG servo frequency is determined by the following formula, applications must
determine the motor speed by setting the number of FG pulses and the crystal oscillator frequency.
fFG(servo) = fOSC/8192
fOSC: The crystal oscillator frequency
2. Direct PWM drive
To minimize power loss in the output, this IC adopts a direct PWM drive technique. The output transistors are always
saturated when on, and motor drive is adjusted by changing the duty with which the output transistors are on. Since
the output switching is performed by the lower side transistors, Schottky diodes (D1, D2, and D3) or similar devices
must be connected between OUT and VCC. (This is because if the devices used do not have a short reverse recovery
time, through currents will flow at the instant the lower side transistors turn on.) Normal rectifying diodes can be used
between OUT and ground.
3. Current limiter circuit
The current limiter circuit operates at a current determined by the formula I = 0.5/Rf, and operates as a peak current
limiter. Its current limiting operation consists of reducing the duty with which the output is on to suppress the current
drawn. No phase compensation capacitors are required.
4. Speed lock range
The speed lock range is ±6.25% of the set speed. When the motor speed is in the lock range the LD pin goes low.
(The LD pin is an open-collector output.) If the motor speed goes out of the lock range, the motor drive output on
duty is modified according to the speed error. This controls the motor speed to be in the lock range.
5. PWM frequency
The PWM frequency is determined by the resistor (R3) and the capacitor (C6) connected to the CR pin.
If R3 is connected to the 4-V fixed-voltage supply:
fPWM ≈ 1/(1.2 × C × R)
If R3 is connected to the 7-V fixed-voltage supply:
fPWM ≈ 1/(0.5 × C × R)
No. 5679-5/10
LB1922
The following formula gives the relationship between the crystal oscillator frequency (fOSC) and the FG frequency fFC.
fFC (servo) = fOSC/(ECL divided by 16 times the number of counts)
= fOSC/8192
External Crystal Oscillator Circuit
External Constants (Provided for reference only.)
However, a crystal with a ratio between the impedance at the crystal
fundamental frequency fo and the impedance at the third harmonic
frequency (3fo) of at least 1:5 must be used.
Xtal (MHz)
C1 (pF)
C2 (pF)
R (k
)
3 to 4
39
82
0.82
4 to 5
39
82
1.0
5 to 7
39
47
1.5
7 to 10
39
27
2.0
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