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参数资料
| 型号： | LB1955 |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 1 A, PDSO28 |
| 封装： | HSOP-28 |
| 文件页数： | 2/9页 |
| 文件大小： | 131K |
| 代理商： | LB1955 |
No. 5452-2/9
LB1955
Electrical Characteristics at Ta = 25°C, VCC = 12 V
Note: * is provided for when X is the peak value at the 60° position of the lower side of the UIN1 Hall amplifier input: THPG = 1.17X.
However, note that the THPG level may be reduced if the value of the capacitor (SH) used for the sample-and-hold circuit is too small since
a discharge current of a few nA will result.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Power Supply]
Current drain
ICC
VC = 0 V, LCTR = 6 V
7.0
10.0
13.0
mA
IC internal power supply
VREF
4.75
5.0
5.25
V
[Output]
Output saturation voltage
VO(sat)1
IO = 400 mA
Sink side
0.4
V
VC = 5 V, Rf = 0
Source side
1.5
V
Output saturation voltage 2
VO(sat)2
IO = 800 mA
Sink side
0.7
V
VC = 5 V, Rf = 0
Source side
2.0
V
3-phase output current ripple
Ior
IO = 100 mA, Rf = 0.47
–5
+5
%
[Hall Amplifier]
Input offset voltage
VHoff
–20
+20
mV
Input bias current
IHb
VAGC = 1.4 V
UIN
10
A
VIN, WIN
5
A
Common-mode input voltage range
VHCM
2.2
5.0
V
[Control]
VC pin input bias current
IVCb
VC = 0 V
–10
–1.3
A
Control start voltage
VTHVC
Rf = 0.47 , IO ≥ 10 mA
2.25
2.5
2.75
V
With the Hall input logic fixed
Open-loop control gain
GMVC
Rf = 0.47 , IO = 200 mA
0.72
0.9
1.08
A/V
With the Hall input logic fixed and VG shorted to RF
[PG]
PG Hall amplifier
VPGoff
Design target
–10
+10
mV
input offset voltage
Peak hold charge current
ISHCHG
(U, V, W) = (L, L, H)
30
A
PG comparator threshold
THPG
SH = 1000pF, Design target*
113
117
121
%
PG output high-level voltage
VPGH
4.5
5.2
V
PG leakage current
ILEAKPG
–10
0
+10
A
[FG]
Back emf Schmitt input
VSCHG
In the back emf Schmitt input increasing direction, Design target
100
mV
hysteresis width
In the back emf Schmitt input decreasing direction, Design target
0
mV
Ringing canceller Schmitt
VSCHR
In the Schmitt input increasing direction, Design target
180
mV
input hysteresis width
In the Schmitt input decreasing direction, Design target
–20
0
+20
mV
FG output high-level voltage
VFGH
FGR = 0 V
4.5
5.2
V
FG leakage current
ILEAKFG
–10
0
+10
A
[TSD]
Thermal shutdown
TTSD
Design target
180
°C
operating temperature
Thermal shutdown
TSD
Design target
15
°C
temperature hysteresis width
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