
LB8109M
No. 5233-3/9
Parameter
Symbol
Conditions
min
typ
max
Unit
Negative/positive transfer gain
difference
GIN
RL =10
–1.0
0
+1.0
dB
Input dead zone voltage range
VDZ
RL =10 , output voltage difference 5 mV or less
030
mV
G-SELECT pin low-gain side
selection voltage
VGSELL-TH
2.0
V
G-SELECT pin high-gain side
selection voltage
VGSELL-TH
1.0
V
[SLED Drive Circuit]
SL REF pin input voltage
range
VSL REF
VASP REF+0.1
VCD–1.0
V
SL REF pin input bias current
IB SL REF
VSL REF = 2 V
200
nA
Positive side setting offset
voltage between IN4
Voff SL REF
VSL REF = 2.3 V, VASP REF = 2 V
–20
+20
mV
and SL REF
Dual side step width difference
voltage
VSL DIFF
VSL REF = 2.3 V, VASP REF = 2 V
–25
+25
mV
SL MODE pin high voltage
VH SL MODE
2.0
V
SL MODE pin low voltage
VL SL MODE
1.0
V
[Muting Block]
Mute on voltage
VON MUTE
2.0
V
Mute off voltage
VOFF MUTE
1.0
V
[OP Amplifier Block]
Input offset voltage
VOFF OP
–5
+5
mV
Input bias current for each
input
IB OP
OPin(+) = OPin(–)= 2 V
200
nA
Common-mode input voltage
range
VCM OP
VCD–1.5
V
Open-loop voltage gain
GV OP
at f =10 kHz
31
34
37
dB
[External Voltage Input Block]
Minimum operating input
voltage when external voltage
VI EXT
RIN =1 k
8.0
V
input is applied
EXTDRV pin output current
IO EXT DRV
VEXT = 1 V (CHG-ON [L])
170
210
250
A
VZ pin voltage
VZ
VEXT =10 V, RIN =1 k
6.4
6.9
7.4
V
VZ pin inflow current
IVZ
20
mA
VEXT, VEXT-CHG pin
IB EXTCHG
VEXT = 1.5 V
Input bias current
IB EXT
VEXT-CHG = 1.5 V (CHG-ON [H])
200
nA
VEXT, VEXT-CHG pin
VrefE-CHG
Both determined at EXTDRV pin
Step-up circuit reference
Vref EXT
EXT-CHG side: CHG-ON [H]
1.23
1.28
1.33
V
voltage
EXTBASE pin saturation
voltage
VEXTBASE
IO = 1 mA
0.2
V
[OSC Block]
OSCPWR pin output voltage
VOSCPWR
VCC–0.15
V
Maximum oscillation frequency
FOSC max
100
kHz
Input bias current
IB OSC
VOSC = 0 V
–2.0
A
[Pulse Charging Function]
Internal reference voltage
VCHG REF
0.32
0.35
0.38
V
CHG-ON pin ON voltage
VCHG-ON
2.0
V
CHG-ON Pin OFF voltage
VCHG-OFF
1.0
V
CHG-MON pin input bias
current
IB CHG MON
VCHG MON = 0.3 V
200
nA
CHGDRV pin output current
IO CHG DRV
VCHG MON = 0 V
2.4
3.0
3.6
mA
[TSD Block]
Operating temperature
TTSD
Design target value, Note 1
180
°C
Temperature hysteresis width
TTSD
Design target value, Note 1
20
°C
Ratings
Continued from preceding page.
Note 1: For parameters which have an entry of ‘‘design target value’’ in the ‘‘Conditions’’ column, no measurements are made.