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参数资料
| 型号： | LC07410LG |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA40 |
| 封装： | 4.40 X 3.60 MM, FLGA-40 |
| 文件页数： | 2/22页 |
| 文件大小： | 473K |
| 代理商： | LC07410LG |
LC07410LG
No.A1345-10/36
Interface Timing Characteristics
Ratings
Parameter
Symbol
min
typ
max
unit
Microcontroller serial interface timing
SCLK cycle time
tCYC
4T
8T
ns
SCLK high period
tSH
2T
4T
ns
SCLK low period
tSL
2T
4T
ns
Data setup time
tSU
2T
4T
ns
Data hold time
tHD
2T
4T
ns
CSX rise to SCLK wait time
tWSCLK
0T
2T
ns
SCLK to CSX rise wait time
tWCSX
4T
6T
ns
Rise time
tSR
50
ns
Fall time
tSF
50
ns
Audio data timing
Clock phase (Note 2)
tPH
75
ns
Clock phase (Note 3)
tPH
1/(128fs)
ns
Data delay time
tDD
0
75
ns
Data setup time
tSUA
1T
ns
Data hold time
tHDA
1T
ns
Note 1: T = 1/fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK = 10MHz, T = 100ns, 2T = 200ns
Note 2: LRCK and BCLK are inputs in Slave mode.
The MCLK timing needs only to be synchronized with LRCK and BCLK and its phase is irrelevant.
Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency.
Note 4: The load of output pin: 30pF.
Microcontroller Serial Interface Timing Diagram
tWSCLK
CSB
SCK
A[7]
tSH
tSL
tCYC
tSU tHD
tSF
tSR
Dn[0]
tWCSX
SDA
Audio Data Timing Diagram
tPH
LRCK
BCLK
ADOUT
tPH
tDD
tSU
tHD
DAIN
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