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参数资料
| 型号： | LC4064ZC-75TN48E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 9/99页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 64MACROCELLS 48TQFP |
| 标准包装： | 250 |
| 系列： | ispMACH® 4000Z |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 1.7 V ~ 1.9 V |
| 逻辑元件/逻辑块数目： | 4 |
| 宏单元数： | 64 |
| 输入/输出数： | 32 |
| 工作温度： | -40°C ~ 130°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists
of the following elements:
? Output Routing Multiplexers
? OE Routing Multiplexers
? Output Routing Pool Bypass Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
OE Routing Multiplexer
From PTOE
5-PT Fast Path
From Macrocell
ORP
Bypass
Multiplexer
OE
To I/O
Cell
To I/O
Cell
Output
Output Routing Multiplexer
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4064ZC-75TN48I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4064ZC-EV | 功能描述:可编程逻辑 IC 开发工具 Eval Board for MACH4064ZC RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| LC4064ZE4MN100C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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