参数资料
型号: LC4512B-10FTN256I
厂商: Lattice Semiconductor Corporation
文件页数: 11/99页
文件大小: 0K
描述: IC CPLD 512MACROCELLS 256FTBGA
标准包装: 90
系列: ispMACH® 4000B
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 2.3 V ~ 2.7 V
逻辑元件/逻辑块数目: 32
宏单元数: 512
输入/输出数: 208
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-FTBGA(17x17)
包装: 托盘
Lattice Semiconductor
Table 10. ORP Combinations for I/O Blocks with 12 I/Os
ispMACH 4000V/B/C/Z Family Data Sheet
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t CO .
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
Figure 8. I/O Cell
GOE 0
GOE 1
GOE 2
GOE 3
From ORP
VCC
V CCO
V CCO
From ORP
*
*
*
To Macrocell
To GRP
*Global fuses
Each output supports a variety of output standards dependent on the V CCO supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V CCO supplied to its I/O bank. The I/O standards supported are:
11
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