参数资料
型号: LC51024VG-75F484C
厂商: Lattice Semiconductor Corporation
文件页数: 4/99页
文件大小: 0K
描述: IC XPLD 1024MC 7.5NS 484FPBGA
标准包装: 60
系列: ispMACH™ 5000VG
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 32
宏单元数: 1024
输入/输出数: 304
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 484-BBGA
供应商设备封装: 484-FPBGA(23x23)
包装: 托盘
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
8
Macrocell
The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks
and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP.
Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output
capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function
for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O
cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be
clocked from one of several global or product term clocks available on the device. A global and product term clock
enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset
for the macrocell register is provided from both global and product term signals. The macrocell register can be pro-
grammed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell.
Figure 8. Macrocell
Memory Modes
The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in
Table 4. The remainder of this section details operation of each of the memory modes. Additional information
regarding the memory modes can also be found in TN1030, Using Memory in ispXPLD 5000MX Devices.
PTSA Bypass
From
I/O Cell
Output to
I/O Block
GRP
PT Clock
From PTSA
PT Preset
PT Reset
Shared PT Reset
Shared
PT CE
CLK0
CLK1
Shared PT Clock
CLK2
CLK3
Global Reset
Clk En
Clk
R/L
D
PR
Q
SELECT
DEVICES
DISCONTINUED
相关PDF资料
PDF描述
NDL2405SC CONV DC/DC 2W 24VIN 5VOUT SIP
GCM12DCMI-S288 CONN EDGECARD 24POS .156 EXTEND
VI-2TZ-CY-F2 CONVERTER MOD DC/DC 2V 20W
HSC44DRES-S13 CONN EDGECARD 88POS .100 EXTEND
VE-B50-CX-B1 CONVERTER MOD DC/DC 5V 75W
相关代理商/技术参数
参数描述
LC51024VG-75F484I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC51024VG-75F676C 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC51024VG-75F676I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC511 制造商:SEOUL 制造商全称:Seoul Semiconductor 功能描述:RED OVAL LAMP LED
LC511-200/N 制造商:Newport Electronics Inc 功能描述:SENSOR, LOAD CELL, 200LB, 3MV/V, Load Capacity:200lb, Cell Output mV / V:3, External Depth:25mm, Length:121mm, Operating Temperature Min:-34C, Operating Temperature Max:82C, Supply Voltage:15VDC , RoHS Compliant: Yes