参数资料
型号: LC5512MV-75QN208C
厂商: Lattice Semiconductor Corporation
文件页数: 8/99页
文件大小: 0K
描述: IC CPLD 512MACROCELLS 208PQFP
标准包装: 24
系列: ispXPLD® 5000MV
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 16
宏单元数: 512
输入/输出数: 149
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
包装: 托盘
其它名称: 220-1728
LC5512MV-75QN208C-ND
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
12
Single-Port SRAM Mode
In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports
accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows
the block diagram of the single-port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock
enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals.
Figure 11. Single-Port SRAM Block Diagram
Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
Clock Enable
CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired.
68 Inputs
from
Routing
RESET
CLK0
CLK3
CLK1
CLK2
16,384-Bit
SRAM
Array
Clock (CLK)
Read/Write Address
(AD[0-8:13])
Write/Read (WR)
Chip Select (CS0,1)
Reset (RST)
Clk Enable (CEN)
Write Data
(DI[0-0,1,3,7,15,31])
Read Data
(DO[0-0,31])
SELECT
DEVICES
DISCONTINUED
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