参数资料
型号: LC5768MB-5F484C
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
中文描述: EE PLD, 6 ns, PBGA484
封装: FPBGA-484
文件页数: 8/95页
文件大小: 923K
代理商: LC5768MB-5F484C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
16
Figure 15. PLL Block Diagram
Figure 16. Connection of Optional PLL Inputs and Outputs
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to TN1003, sysCLOCK PLL Usage Guide for ispXPGA, ispGDX2, ispXPLD
SEC_OUT
CLK_OUT
PLL_LOCK
CLK_IN
PLL_RST
PLL_FBK
Input Clock
(M) Divider
Post-scalar
(V) Divider
VCO
and
Phase
Detector
Programable
Delay
Secondary
Clock
(K) Divider
Feedback
Loop
(N) Divider
Clock Net
PLL_LOCK
To GRP
CLK_OUT
From Macrocell
To GRP
PLL_RST
From Macrocell
To GRP
PLL_FBK
From Macrocell
I/O Pin*
*See pinout table for details
相关PDF资料
PDF描述
LC5512MB-75F484C
LC5768MB-75F484I
LC5768MC-75F484I
LC5512MB-75F484I
LC5768MB-5F256C
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