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参数资料
| 型号： | LC72133V |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封装： | SSOP-20 |
| 文件页数： | 14/23页 |
| 文件大小： | 147K |
| 代理商： | LC72133V |
Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of
this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularly-
priced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
signal.
Figure 4
Figure 5
2. Notes on the FMIN, AMIN, and IFIN Pins
Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is
desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will
increase and incorrect counting may occur due to the relationship with the wait time.
3. Notes on IF Counting
→ SD must be used in conjunction with the IF counting time
When using IF counting, always implement IF counting by having the microprocessor determine the presence of the
IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which
auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is
no signal due to leakage output from the IF counter buffer.
4. DO Pin Usage Techniques
In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for
unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the
controller.
5. Power Supply Pins
A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion.
This capacitor must be placed as close as possible to the VDD and VSS pins.
6. VCO setup
Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune)
goes to 0V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily
force Vtune to VCC to prevent the deadlock from occuring. (Deadlock clear circuit)
7. Front end connection example
Since this product is designed with the relatively high resistance of 200 k
for the pull-down (on) resistors built in to
the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit.
No. 5427-21/23
LC72133M, 72133V
Reference Divider
fr
Programmable Divider
fp
Phase
Detector
LPF
VCO
MIX
RF
A11940
A11941
(A)
(B)
(ns)
Dead Zone
V
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