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参数资料
| 型号： | LC72140 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 2/15页 |
| 文件大小： | 321K |
| 代理商： | LC72140 |
LC72140, 72140M
No.4464–10/15
Serial Data Output
The 40-bit data word output on DO has the format and functions as shown in Figure 6 and Table 12, respectively.
Figure 6. Output data word OUT
Table 12. Input data functions
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Serial Data Output Timing
The timing for the serial data output is shown in figure 7. The first eight bits are the mode select bits.
Figure 7. Output timing
Notes
1. tSU, tHD, tEL, tES, tCL and tCH>0.45s
2. tDC and tDH<0.2s
3. Since DO is an open-drain output, the data transition time depends on the value of the pull-up resistor.
4. DO is normally open.
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