参数资料
型号: LC72148V
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封装: SSOP-24
文件页数: 2/21页
文件大小: 170K
代理商: LC72148V
No. 6974-10/21
LC72148V
Continued from preceding page.
Number
Control block/data
Description
Related data
This data selects the output from the DO pin.
*1. end-UC is the general-purpose counter measurement complete check function.
(1) When end-UC is set and the counter started (CTE = 0
→ 1), the DO pin automatically goes to
the open state.
(2) When the general-purpose counter measurement completes, the DO pin goes to the low
level, and it becomes possible to check for the count complete state.
(3) The DO pin goes to the open state due to the I/O of serial data (when the CE pin is high).
*2
However, when the I/O-1 and I/O-2 pins are specified to be output ports, IN will go to the open
state.
*3: This is invalid if the I/O-5 pin is specified to be an input port.
Note: The DO pin will be in the open state, regardless of the state of the DO pin control data,
during the data input period (the period when CE is high in IN1 or IN2 mode).
Furthermore, the DO pin will output the content of the internal DO serial data in
synchronization with CL, regardless of the state of the DO pin control data during the data
output period (the period when CE is high in OUT mode).
DO cannot be used (it does not change state) in crystal oscillator stopped mode (R0=0,
R1=R2=R3=1).
Don’t Care
CTE
OUT5
I/O-1
I/O-2
I/O-5
(4)
DO and I/O-5 pin control
data
ULD
DT0, DT1
IL0, IL1
(5)
*
ULD
DT1
DT0
DO pin state
I/O-5 pin state
0
Low when the unlocked state
is detected.
0
1
Open
OUT5 *3
0
1
0
end-UC *1
0
1
IN *2
1
0
Open
1
0
1
Open
Low when the unlocked state
is detected. *3
1
0
end-UC *1
1
IN *2
(1) Counting starts
(2) Counting completes
(3) CE: HI
DO pin
IL1
IL0
IN
0
Open
0
1
I-1 (pin state)
1
0
I-2 (pin state)
1
DO goes low when I-1 changes state.
Continued on next page.
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