- 您现在的位置：买卖IC网 > PDF目录30732 > LC7471 ON-SCREEN DISPLAY IC, PDIP22 PDF资料下载
参数资料
| 型号： | LC7471 |
| 元件分类： | 画面叠加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP22 |
| 封装： | SHRINK, DIP-22 |
| 文件页数： | 8/12页 |
| 文件大小： | 134K |
| 代理商： | LC7471 |
LC7471
No.4088–5/12
RAM Memory Configuration
RAM memory is organized as 16-bit words as shown in
the following table. Locations 000H to 0AFH are display
RAM, locations 0B0H through to 0BBH are display line
Note
× = don’t care
address registers, locations 0BCH to 0BDH are display con-
trol registers, location 0BEH is the video signal control reg-
ister and location 0BFH is the general control register.
s
e
r
d
A
s
t
n
e
t
n
o
c
y
r
o
m
e
M
n
o
i
t
p
i
r
c
s
e
D
F
E
D
C
B
A
9876543210
o
t
H
0
H
F
A
0
00000000
L
F0
C5
C4
C3
C2
1
CC0
r
e
t
c
a
r
a
h
c
t
i
b
-
6
h
t
i
w
M
A
R
y
a
l
p
s
i
D
t
i
b
e
l
b
a
n
e
g
n
i
h
s
a
l
f
d
n
a
e
d
o
c
H
0
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
1
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
1
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
2
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
2
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
3
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
3
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
4
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
4
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
5
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
5
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
6
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
6
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
7
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
7
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
8
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
8
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
9
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
9
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
0
1
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
A
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
1
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
B
0
00000
A
R
D
A9
R
D
A8
R
D
A7
R
D
A6
R
D
A5
R
D
A4
R
D
A3
R
D
A2
R
D
A1
R
D
A0
R
D
A
t
s
r
i
f
o
M
O
R
y
a
l
p
s
i
d
n
i
s
e
r
d
A
2
1
e
n
i
l
f
o
r
e
t
c
a
r
a
h
c
H
C
B
0
0000
1
3
Z
S
H0
3
Z
S
H1
2
Z
S
H0
2
Z
S
H1
1
Z
S
H0
1
Z
S
H
5
P
H4
P
H3
P
H2
P
H1
P
H0
P
H
d
n
a
n
o
i
t
i
s
o
p
t
r
a
t
s
y
a
l
p
s
i
d
l
a
t
n
o
z
i
r
H
h
t
d
i
w
l
e
x
i
p
H
D
B
0
0000
1
3
Z
S
V0
3
Z
S
V1
2
Z
S
V0
2
Z
S
V1
1
Z
S
V0
1
Z
S
V
5
P
V4
P
V3
P
V2
P
V1
P
V0
P
V
d
n
a
n
o
i
t
i
s
o
p
t
r
a
t
s
y
a
l
p
s
i
d
l
a
c
v
i
t
r
e
V
t
h
g
i
e
h
l
e
x
i
p
H
E
B
0
0000
/
T
N
I
N
O
N
××
C
S
O
P
T
S
P
S
D
N
O
×
S
Y
S
T
S
R
×××
1
H
P0
H
P
y
a
l
p
s
i
d
,
e
s
a
h
p
l
a
n
g
i
s
o
e
d
i
V
d
n
a
l
o
r
t
n
o
c
r
o
t
a
l
i
c
s
o
,
g
n
i
k
n
a
l
b
n
o
i
t
c
e
l
e
s
t
e
s
e
r
m
e
t
s
y
s
H
F
B
0
0000
T
S
T
D
O
M
××
1
K
L
B0
K
L
B
×
2
L
F1
L
F0
L
FT
X
E
×
L
O
C
B
d
n
a
,
g
n
i
h
s
a
l
f
,
g
n
i
k
n
a
l
b
r
e
t
c
a
r
a
h
C
n
o
i
t
c
e
l
e
s
e
d
o
m
t
s
e
t
Horizontal Display Control Register (0BCH)
The function of each bit in the horizontal display control register is shown in the following table. Note that a LOW-
level pulse on RST resets all bits to 0.
Table 1. Line 1 pixel width
Table 2. Line 2 pixel width
Table 3. Line 3 to line 12 pixel width
t
i
b
a
t
a
De
m
a
N
n
o
i
t
c
n
u
F
00
P
H
n
o
i
t
a
u
q
e
g
n
i
w
o
ll
o
f
e
h
t
y
b
n
e
v
i
g
s
a
,
S
H
,
n
e
r
c
s
e
h
t
n
o
y
a
l
p
s
i
d
e
h
t
f
o
n
o
i
t
i
s
o
p
t
r
a
t
s
l
a
t
n
o
z
i
r
o
h
e
h
t
s
t
c
e
l
e
S
T
e
r
e
h
w
C
T
4
f
o
s
e
l
p
i
t
l
u
m
n
i
s
t
n
e
m
e
r
c
n
i
S
H
t
a
h
t
e
t
o
N
.
r
o
t
a
ll
i
c
s
o
k
c
o
l
c
t
o
d
e
h
t
f
o
d
o
i
r
e
p
e
h
t
s
i
C.
11
P
H
22
P
H
33
P
H
44
P
H
55
P
H
60
1
Z
S
H
.
1
e
l
b
a
t
n
i
n
w
o
h
s
a
h
t
d
i
w
l
e
x
i
p
1
e
n
il
s
t
c
e
l
e
S
71
1
Z
S
H
80
2
Z
S
H
.
2
e
l
b
a
t
n
i
n
w
o
h
s
a
h
t
d
i
w
l
e
x
i
p
2
e
n
il
s
t
c
e
l
e
S
91
2
Z
S
H
A0
3
Z
S
H
.
3
e
l
b
a
t
n
i
n
w
o
h
s
a
h
t
d
i
w
l
e
x
i
p
2
1
e
n
il
o
t
3
e
n
il
s
t
c
e
l
e
S
B1
3
Z
S
H
C–
n
o
i
t
c
n
u
f
o
N
1
Z
S
H0
1
Z
S
Hh
t
d
i
W
00
T
1 C
l
e
x
i
p
/
01
T
2 C
l
e
x
i
p
/
10
T
3 C
l
e
x
i
p
/
11
T
4 C
l
e
x
i
p
/
1
2
Z
S
H0
2
Z
S
Hh
t
d
i
W
00
T
1 C
l
e
x
i
p
/
01
T
2 C
l
e
x
i
p
/
10
T
3 C
l
e
x
i
p
/
11
T
4 C
l
e
x
i
p
/
1
3
Z
S
H0
3
Z
S
Hh
t
d
i
W
00
T
1 C
l
e
x
i
p
/
01
T
2 C
l
e
x
i
p
/
10
T
3 C
l
e
x
i
p
/
11
T
4 C
l
e
x
i
p
/
相关PDF资料 |
PDF描述 |
|---|---|
| LC74721M | ON-SCREEN DISPLAY IC, PDSO24 |
| LC74721 | ON-SCREEN DISPLAY IC, PDIP24 |
| LC74723 | ON-SCREEN DISPLAY IC, PDIP24 |
| LC74723M | ON-SCREEN DISPLAY IC, PDSO24 |
| LC74725 | ON-SCREEN DISPLAY IC, PDIP24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC74711 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Controller LSI for On-screen Displays |
| LC7472 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:On-screen Video Display Controller for NTSC or PAL-M |
| LC74721 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:On-screen Video Display Controllers for NTSC or PAL-M |
| LC74721M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:On-screen Video Display Controllers for NTSC or PAL-M |
| LC74723 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:On-Screen Display Controller |
发布紧急采购，3分钟左右您将得到回复。