参数资料
型号: LC75832W-E
厂商: ON Semiconductor
文件页数: 18/22页
文件大小: 0K
描述: IC LCD DISPLAY DRIVER 64SQFP
标准包装: 50
系列: *
LC75832E, 75832W
Display Control and the INH Pin
Since the IC's internal data (the display data D1 to D54 and the control data when in static drive mode, and the display
data D1 to D108 and the control data when in 1/2 duty drive mode) is undefined when power is first applied,
applications should set the INH pin low at the same time as power is applied to turn off the display (setting S1/P1 to
S4/P4 and S5 to S54, COM1, and COM2 to the VSS level) and during this period send serial data from the controller.
The controller should then set the INH pin high after the data transfer has completed. This procedure prevents
unnecessary display at power on (See Figures 4 to 7).
Notes on the Power On/Off Sequences
Applications should observe the following sequence when turning the LC75832E and LC75832W power on and off.
(See Figures 4 to 7):
? At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on
? At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off
However, if the logic and LCD driver block use a shared power supply, then power supplies can be turned on and off at
the same time.
? Static drive mode
t2
t1
t3
VDD
VLCD
INH
VIL1
tc
CE
D1 to D54,P0 to P2,
Display data and control data transferred
VIL1
Internal data DT, FC0 to FC2,
Undefined
Defined
Undefined
OC, SC, BU
Notes: t1 ≥ 0
t2>0
? Static drive mode (when in 822 mode data transfer)
t1
Figure 4
t2
t3 ≥ 0 (t2>t3)
tc ??? 10 μ s min
t3
VDD
VLCD
INH
VIL1
tc
CE
D1 to D23,
Display data and control data transferred
VIL1
Internal data D25 to D54,
Undefined
Defined
Undefined
DT
Notes: t1 ≥ 0
t2>0
Figure 5
t3 ≥ 0 (t2>t3)
tc ??? 10 μ s min
No.A0712-18/22
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