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参数资料
| 型号： | LC78833M |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 16-BIT DAC, PDSO20 |
| 封装： | MFP-20 |
| 文件页数： | 11/11页 |
| 文件大小： | 293K |
| 代理商： | LC78833M |
Resistor string D/A converter
This 8-bit D/A converter uses a total of 256 (= 28) unit-resistance (R) resistors connected in series to voltage divide
the potential applied to the ends of that resistor string into 256 equal intervals. Of these resistor-divided potentials,
two adjacent potentials, V1 and V2, are selected by a switching circuit according to the value of the upper 8 bits
(D15 to D8) of the data. These two potentials are output to the PWM D/A converter. Note that these potentials are
related as follows:
V2 – V1 = (VH – VL)/256
PWM D/A converter
This 4-bit D/A converter divides (by 16) the interval between the two potentials, V1 and V2, output by the resistor-
string D/A converter. This circuit outputs one or the other of the V1 and V2 potentials from the CH1OUT (or
CH2OUT) pin according to the value of the middle 4 bits (D7 to D4) of the data.
Level shifting D/A converter
This 4-bit D/A converter is implemented by connecting the variable resistors VRH and VRL in series at the ends of
the resistor-string D/A converter. The values of the VRH and VRL variable resistors are modified according to the
value of the low-order 4 bits of the data as follows:
— The value of VRH + VRL is held fixed regardless of the value of the data.
— The values of VRH and VRL are changed in R/256 unit steps (where R is the value of the resistor-string D/A
converter unit resistors) over the range zero to 15R/256.
This causes the resistor-string D/A converter V1 and V2 outputs to change in
V/256 steps (where V = (VH –
VL)/256) over the range 0 to 15
× V/256 according to the value of the lower 4 bits of the data.
— The Vref H/L and REFH/L pins
The Vref H/L pins provide the reference voltage to the resistor string, and are normally connected to AVDD and
AGND, respectively. REFH and REFL are each connected to AGND through a capacitor of about 10 F.
The maximum output amplitude is acquired when Vref H is 5.0 V and Vref L is 0 V. The internal resistors RH
and RL cause the output range to be between 0.7 V (minimum) and 3.5 V (maximum) (2.8 Vp-p) for 0 dB.
Filter Characteristics (as calculated)
4
× oversampling
Ripple: Less than ±0.1 dB
Attenuation: –35 dB or lower
No. 5212-9/11
LC78833M, 78833V
相关PDF资料 |
PDF描述 |
|---|---|
| LC78833V | SERIAL INPUT LOADING, 16-BIT DAC, PDSO24 |
| LC78834M | SERIAL INPUT LOADING, 18-BIT DAC, PDSO28 |
| LC78836M | SERIAL INPUT LOADING, 16-BIT DAC, PDSO24 |
| LC7883K | SERIAL INPUT LOADING, 16-BIT DAC, PDIP28 |
| LC7883KM | SERIAL INPUT LOADING, 16-BIT DAC, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC78833V | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Digital Audio 16-Bit D/A Converter with Built-In Digital Filters |
| LC78834M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Stereo 18-bit Digital Audio D/A Converter with On-Chip 4 fs Digital Filters |
| LC78835 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:18 Bits Digital Filter and D/A Converter for Digital Audio |
| LC78835K | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:18 Bits Digital Filter and D/A Converter for Digital Audio |
| LC78835KM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:18 Bits Digital Filter and D/A Converter for Digital Audio |
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