参数资料
型号: LC87F2932AU-CD-E
厂商: ON Semiconductor
文件页数: 9/29页
文件大小: 0K
描述: IC MCU 8BIT 32K FLASH 64TQLP
标准包装: 250
芯体尺寸: 8-位
速度: 12MHz
连通性: SIO,UART/USART
外围设备: PWM,WDT
输入/输出数: 59
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.2 V ~ 5.5 V
数据转换器: A/D 13x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: *
包装: *
LC87F2932A
No.A1210-17/29
Continued from preceding page.
Parameter
Symbol
Pin/Remarks
Conditions
Specification
VDD[V]
min
typ
max
unit
Power dissipation
Pd max
QIP64E(14
×14)
Ta=-40 to +85
°C
292
mW
TQFP64J(7
×7)
133
FLGA68K(6.0
×6.0)
96
FLGA64(5.0
×5.0)
91
Operating ambient
temperature
Topr
-40
+85
°C
Storage ambient
temperature
Tstg
-55
+125
Allowable Operating Range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
Specification
VDD[V]
min
typ
max
unit
Operating
supply voltage
(Note 2-1)
VDD(1)
VDD1=VDD2=VDD3
0.245s
≤ tCYC ≤ 200s
3.0
5.5
V
0.367s
≤ tCYC ≤ 200s
2.5
5.5
0.681s
≤ tCYC ≤ 200s
2.2
5.5
Memory
sustaining
supply voltage
VHD
VDD1=VDD2=VDD3
RAM and register contents
sustained in HOLD mode.
2.0
5.5
High level input
voltage
VIH(1)
Ports 1, 2
P71 to P73
P70 port input/
interrupt side
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(2)
Ports 0, 3, 8, B, C
PWM2, PWM3
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(3)
Port 70 watchdog
timer side
2.2 to 5.5
0.9VDD
VDD
VIH(4)
XT1, XT2, CF1, CF2,
RES
2.2 to 5.5
0.75VDD
VDD
Low level input
voltage
VIL(1)
Ports 1, 2
P71 to P73
P70 port input/
interrupt side
4.0 to 5.5
VSS
0.1VDD
+0.4
2.2 to 4.0
VSS
0.2VDD
VIL(2)
Ports 0, 3, 8, B, C
PWM2, PWM3
4.0 to 5.5
VSS
0.15VDD
+0.4
2.2 to 4.0
VSS
0.2VDD
VIL(3)
Port 70 watchdog
timer side
2.2 to 5.5
VSS
0.8VDD
-1.0
VIL(4)
XT1, XT2, CF1, CF2,
RES
2.2 to 5.5
VSS
0.25VDD
Instruction cycle
time
(Note 2-2)
tCYC
3.0 to 5.5
0.245
200
μs
2.5 to 5.5
0.367
200
2.2 to 5.5
0.681
200
External system
clock frequency
FEXCF(1)
CF1
CF2 pin open
System clock frequency
division ratio=1/1
External system clock duty
=50
±5%
3.0 to 5.5
0.1
12
MHz
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
4
CF2 pin open
System clock frequency
division ratio=1/2
3.0 to 5.5
0.2
24.4
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
8
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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