3. The following output settings can be controlled:
Channel status (C bit) output
Subcode Q data output
Status ID and shortening ID detection for DAT that use subcodes
C bit output
This function presumes that this IC will be used in consumer mode and thus only handles the first 32 bits.
The flag is fixed at the high level (although there is no flag in the type 1 microprocessor interface timing), and the
data format is LSB first.
Error and update checking is not applied to the data.
The internal shift register is reset if a PLL lock error occurs.
An interval of at least 6 msec must be provided between consecutive data readout operations.
Subcode Q output
Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this
signal falls. However, this signal will not be output (fall) unless 96 bits of subcode Q data (include the CRC check
bits) is input.
The flag outputs a high when the CRC check passes, and low if the CRC check fails.
The bit order is LSB first within each byte of the 80 bits of subcode Q data.
ID detection
The start ID and shortening ID are only detected when the DAT category code (1100000L) is received.
These IDs are detected as follows:
— A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync
signal (L0).
— After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for
subcode Q data to SWDT/DI.
Figure 4 User Data for DAT that Use Subcodes
The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and
the data output.
Output pins
The output scheme used for SRDT/DO differs depending on the microprocessor interface format selected by
CKSEL.
No. 5237-13/16
LC8905V
(L0): SYNC
H
(R0): Start ID
H
L
(L1): Shortening ID
L
H
Flags + 80 data bits
all H
all L
Detected ID
Start ID
Shortening ID
CKSEL
Format
SRDT/DO
L
Figure 2
Open-drain output
H
Figure 3
Three-state output