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参数资料
| 型号： | LC89950 |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP14 |
| 封装： | DIP-14 |
| 文件页数： | 2/5页 |
| 文件大小： | 98K |
| 代理商： | LC89950 |
No. 5440-2/5
LC89950
Electrical Characteristics at Ta = 25°C, VDD = 5.0 V, Fscp = 15.625 kHz
Parameter
Symbol
Switch States
min
typ
max
Unit
Test
SW1
SW2
SW3
SW4
conditions
Current drain
IDD
a/b
a
a/b
1
5
10
15
mA
Output pin voltage (pin 1)
VOUT (R-Y)
b
a
a/b
2
0.7
1.7
2.7
V
Output pin voltage (pin 3)
VOUT (B-Y)
a
a/b
2
0.7
1.7
2.7
V
Input pin voltage (pin 7)
VIN (R-Y)
b
a
a/b
2
1.4
2.4
3.4
V
Input pin voltage (pin 5)
VIN (B-Y)
a
a/b
2
1.4
2.4
3.4
V
Voltage gain
GV (R-Y)
a
3
–2
0
+2
dB
GV (B-Y)
b
a
3
–2
0
+2
dB
Differential voltage gain
G
V
a
b
a
3
0.1
0.3
dB
Frequency characteristics
Gf (R-Y)
a
4
–3
–1
dB
Gf (B-Y)
b
a
4
–3
–1
dB
Positive phase input linearity +L6
+L6 (R-Y)
a
b
5
57
60
63
%
+L6 (B-Y)
b
a
b
5
57
60
63
%
Inverted input linearity
–L6
–L6 (R-Y)
a
b
5
57
60
63
%
–L6 (B-Y)
b
a
b
5
57
60
63
%
Clock leakage (4 MHz)
Lclk (R-Y)
a
6
7
12
mVrms
Lclk (B-Y)
b
a
6
7
12
mVrms
Noise level
No (R-Y)
a
b
7
1
2
mVrms
No (B-Y)
b
a
b
7
1
2
mVrms
Output impedance
ZOUT (R-Y)
a
b
a
8
200
300
400
ZOUT (B-Y)
b
a
b
a
8
200
300
400
Delay time
Td (R-Y)
a
9
63.80
s
Td (B-Y)
b
a
9
63.80
s
Sandcastle Pulse (Input Clock) Conditions
Notes: 1. Indicates the synchronization range for the PLL circuit. The delay time changes with the input frequency.
2. Vhigh is the minimum value between c and d.
3. Vmid is the maximum value between a and b and between e and f.
Parameter
Symbol
Conditions
min
typ
max
Unit
Input frequency*1
Fscp
14.625
15.625
16.625
kHz
Input pulse width
TW bgp
3.0
4.0
5.0
s
High level*2
Vhigh
5.9
6.5
7.5
V
Mid level*3
Vmid
2.5
3.5
4.4
V
Low level
Vlow
–0.3
0
2.5
V
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