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参数资料
| 型号： | LC99052-V64A |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 3/8页 |
| 文件大小： | 124K |
| 代理商： | LC99052-V64A |
Pin Functions
I/O
→ I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
No. 5072-3/8
LC99052-V64A
Pin No.
Symbol
I/O
Function
1
VDD1 (AMOS-A)
2
CCDIN
I
CCD input pin
3
CAP1
I
AMOS-CDS bias pin
4
AMPIN
I
6 dB amplifier input pin
5
CLAMPDC
O
6 dB amplifier clamp circuit bias output pin
6
GOUT
O
Gain control output
7
GAININ
I
Gain control input
8
AMPOUT
O
6 dB amplifier output pin
9
CAPA2
I
AMOS-AGC bias pin
10
YOUT
O
AGC output
11
YIN
I
Clamp, A/D converter input
12
CAPB2
I
AMOS-clamp bias pin
13
TOAMPDC
O
6 dB amplifier bias output pin
14
VSS1 (AMOS-A)
15
VDD2 (ADC-A)
16
REFHIN
I
A/D converter high level reference input
17
REFLIN
I
A/D converter low level reference input
18
REFH
O
A/D converter high level reference output
19
REFM
O
A/D converter middle level reference output
20
REFL
O
A/D converter low level reference output
21
VSS2 (ADC-A)
22
VSS3 (ADC-D)
23
VDD3 (ADC-D)
EXT1, 2 = 00: Direct H and V reset, 10: Direct C.sync reset
24
EXT1
I
01: Mode 3, an external clamp pulse can be input from pin 32 (VR), ENDFLG is output from
pin 36 (CSYNC).
11: NON
25
EXT2
I
26
EXT3
I
EXT3, 4 = 00: Auto iris, 10: Normal, 01: External shutter, 11: External FT, ST
27
EXT4
I
28
CLKS
I
Serial clock input
29
DATAS
I
Serial data input
30
REGRESB
I
Register reset; 0: Reset
31
HR
I
Hsync, CSYNC reset pulse input
32
VR
I
Vsync reset pulse input
33
FTTRG
I
External frame_sift trigger input
Auto iris mode = selmet1
34
STTRG
I
External shutter trigger input
Auto iris mode = selmet2
35
CSYNC
O
In mode 3 (H reset mode), this pin outputs ENDFLG.
This pin is affected by the SSG_DELAY (register).
36
HD
O
This pin is affected by the SSG_DELAY (register).
37
VD
O
This pin is affected by the SSG_DELAY (register).
38
FLD
O
This pin is affected by the SSG_DELAY (register). Outputs a video output frame index pulse in long
exposure mode.
39
IREF1
I
Automatic iris and AGC hold; 1: Hold, 0: Active
40
VSS6 (DATA)
41
VDD6 (DATA)
42
IREF2
I
Automatic iris fine adjustment; 1: Bright, 0: Normal
43
VREFIN
I
D/A converter reference voltage input
44
VDD5 (DAC-A)
45
VSS5 (DAC-A)
46
VIDEO
O
D/A converter output (video output)
47
COMP
O
D/A converter bias pin
48
IREFOUT
O
D/A converter reference voltage output
49
VSS4 (DAC-D)
50
VDD4 (DAC-D)
Continued on next page.
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