参数资料
型号: LCMXO1200C-3M132C
厂商: Lattice Semiconductor Corporation
文件页数: 18/88页
文件大小: 0K
描述: IC PLD 1200LUTS 101I/O 132-BGA
标准包装: 360
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 5.1ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 600
输入/输出数: 101
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 132-LFBGA,CSPBGA
供应商设备封装: 132-CSPBGA(8x8)
包装: 托盘
Architecture
MachXO Family Data Sheet
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. MachXO PIO Block Diagram
From Routing
From Routing
TS
sysIO
TSALL
TO
Buffer
Fast Output
Data signal
DO
PAD
1
Input
Data Signal
Programmable
Delay Elements
2
3
+
4 -
Note: Buffer 1 tracks with V CCAUX
Buffer 2 tracks with V CCIO.
Buffer 3 tracks with internal 1.2V V REF.
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
From Complementary
Pad
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V CCIO . In addition to the Bank V CCIO supplies, the MachXO devices have a V CC core logic power supply,
and a V CCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buf-
fers.
MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with
complementary outputs on all the I/O Banks.
MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pairs ?
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
2-15
相关PDF资料
PDF描述
EMC35DRYS-S93 CONN EDGECARD 70POS DIP .100 SLD
TAP105K035HSB CAP TANT 1UF 35V 10% RADIAL
XC2C512-10PQG208C IC CRII CPLD 512MCRCELL 208PQFP
VE-24X-EV-F2 CONVERTER MOD DC/DC 5.2V 150W
RS2J-13-F DIODE FAST REC 600V 1.5A SMB
相关代理商/技术参数
参数描述
LCMXO1200C-3M132I 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 101 IO 1.8 /2.5/3.3V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-3MN132C 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 101 IO 1.8 /2.5/3.3V -3 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-3MN132I 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 101 IO 1.8 /2.5/3.3V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-3T100C 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 73 IO 1.8/ 2.5/3.3V -3 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-3T100I 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 73 IO 1.8/ 2.5/3.3V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100