3-14
DC and Switching Characteristics
Lattice Semiconductor
MachXO Family Data Sheet
MachXO Internal Timing Parameters
1
Over Recommended Operating Conditions
Parameter
Description
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
PFU/PFF Logic Mode Timing
tLUT4_PFU
LUT4 delay (A to D inputs to F output)
—
0.28
—
0.34
—
0.39
ns
tLUT6_PFU
LUT6 delay (A to D inputs to OFX output)
—
0.44
—
0.53
—
0.62
ns
tLSR_PFU
Set/Reset to output of PFU
—
0.90
—
1.08
—
1.26
ns
tSUM_PFU
Clock to Mux (M0,M1) input setup time
0.10
—
0.13
—
0.15
—
ns
tHM_PFU
Clock to Mux (M0,M1) input hold time
-0.05
—
-0.06
—
-0.07
—
ns
tSUD_PFU
Clock to D input setup time
0.13
—
0.16
—
0.18
—
ns
tHD_PFU
Clock to D input hold time
-0.03
—
-0.03
—
-0.04
—
ns
tCK2Q_PFU
Clock to Q delay, D-type register configuration
—
0.40
—
0.48
—
0.56
ns
tLE2Q_PFU
Clock to Q delay latch configuration
—
0.53
—
0.64
—
0.74
ns
tLD2Q_PFU
D to Q throughput delay when latch is enabled
—
0.55
—
0.66
—
0.77
ns
PFU Dual Port Memory Mode Timing
tCORAM_PFU
Clock to Output
—
0.40
—
0.48
—
0.56
ns
tSUDATA_PFU Data Setup Time
-0.18
—
-0.22
—
-0.25
—
ns
tHDATA_PFU
Data Hold Time
0.28
—
0.34
—
0.39
—
ns
tSUADDR_PFU Address Setup Time
-0.46
—
-0.56
—
-0.65
—
ns
tHADDR_PFU
Address Hold Time
0.71
—
0.85
—
0.99
—
ns
tSUWREN_PFU Write/Read Enable Setup Time
-0.22
—
-0.26
—
-0.30
—
ns
tHWREN_PFU Write/Read Enable Hold Time
0.33
—
0.40
—
0.47
—
ns
PIO Input/Output Buffer Timing
tIN_PIO
Input Buffer Delay
—
0.75
—
0.90
—
1.06
ns
tOUT_PIO
Output Buffer Delay
—
1.29
—
1.54
—
1.80
ns
EBR Timing (1200 and 2280 Devices Only)
tCO_EBR
Clock to output from Address or Data with no output
register
—
2.24
—
2.69
—
3.14
ns
tCOO_EBR
Clock to output from EBR output Register
—
0.54
—
0.64
—
0.75
ns
tSUDATA_EBR Setup Data to EBR Memory
-0.26
—
-0.31
—
-0.37
—
ns
tHDATA_EBR
Hold Data to EBR Memory
0.41
—
0.49
—
0.57
—
ns
tSUADDR_EBR Setup Address to EBR Memory
-0.26
—
-0.31
—
-0.37
—
ns
tHADDR_EBR
Hold Address to EBR Memory
0.41
—
0.49
—
0.57
—
ns
tSUWREN_EBR Setup Write/Read Enable to EBR Memory
-0.17
—
-0.20
—
-0.23
—
ns
tHWREN_EBR Hold Write/Read Enable to EBR Memory
0.26
—
0.31
—
0.36
—
ns
tSUCE_EBR
Clock Enable Setup Time to EBR Output Register
0.19
—
0.23
—
0.27
—
ns
tHCE_EBR
Clock Enable Hold Time to EBR Output Register
-0.13
—
-0.16
—
-0.18
—
ns
tRSTO_EBR
Reset To Output Delay Time from EBR Output Regis-
ter
—
1.03
—
1.23
—
1.44
ns
PLL Parameters (1200 and 2280 Devices Only)
tRSTREC
Reset Recovery to Rising Clock
1.00
—
1.00
—
1.00
—
ns
tRSTSU
Reset Signal Setup Time
1.00
—
1.00
—
1.00
—
ns
1. Internal parameters are characterized but not tested on every device.
Rev. A 0.19