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参数资料
| 型号： | LCMXO640C-5T144C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | FLASH PLD, 3.5 ns, PQFP144 |
| 封装： | 20 X 20 MM, TQFP-144 |
| 文件页数： | 78/96页 |
| 文件大小： | 1389K |
| 代理商： | LCMXO640C-5T144C |
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2-5
Architecture
Lattice Semiconductor
MachXO Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A
LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by program-
ming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger
lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Ripple mode multiplier building block
Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the
software will construct these using distributed memory primitives that represent the capabilities of the PFU.
Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows
the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice
functions as the read-write port, while the other companion Slice supports the read-only port. For more information
on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data
sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
Logic
Ripple
RAM
ROM
PFU Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
SP 16x2
ROM 16x1 x 2
PFF Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
N/A
ROM 16x1 x 2
SPR16x2
DPR16x2
Number of Slices
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
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相关代理商/技术参数 |
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| LCMXO640C-5TN100C | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTS 74 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640C-5TN100C4W | 制造商:Lattice Semiconductor Corporation 功能描述:MACHXO PLD FLASH SCRAM 1.8V 640 |
| LCMXO640C-5TN144C | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTS 113 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640C-5TN144C4W | 制造商:Lattice Semiconductor Corporation 功能描述:MACHXO PLD FLASH SCRAM 1.8V 640 |
| LCMXO640C-L-EV | 功能描述:可编程逻辑 IC 开发工具 MachXO 640 Eval Brd Standard RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
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