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参数资料
| 型号： | LF2250QC20 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 12 x 10-bit Matrix Multiplier |
| 中文描述： | 12-BIT, DSP-MULTIPLIER, PQFP120 |
| 封装： | PLASTIC, QFP-120 |
| 文件页数： | 13/15页 |
| 文件大小： | 369K |
| 代理商： | LF2250QC20 |
DEVICES INCORPORATED
LF2250
12 x 10-bit Matrix Multiplier
Video Imaging Products
13
08/16/2000–LDS.2250-L
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Never-
theless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above
V
CC
will be clamped beginning at –0.6 V and
V
CC
+ 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary
from those designated but operation is
guaranteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated
by:
NCV F
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of
I
OH
and
I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 μF ceramic capacitor should be
installed between
V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device
V
CC
and the tester common, and device
ground and tester common.
b. Ground and
V
CC
supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and
V
CC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses
from the internal circuitry are specified
from the point of view of the device.
Output delay, for example, is specified
as a maximum since worst-case opera-
tion of any device always provides data
within that time.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.0V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
S1
I
OH
I
OL
V
TH
C
L
DUT
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
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