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参数资料
| 型号： | LF43891 |
| 厂商： | Logic Devices Incorporated |
| 英文描述： | 9 x 9-bit Digital Filter |
| 中文描述： | 9 × 9位数字滤波器 |
| 文件页数： | 4/11页 |
| 文件大小： | 79K |
| 代理商： | LF43891 |
DEVICES INCORPORATED
LF43891
9 x 9-bit Digital Filter
Video Imaging Products
08/16/2000–LDS.43891-J
4
OUTPUT STAGE DESCRIPTION
The 26-bit adder contained in the
output stage can add the contents of
any filter cell accumulator (selected by
ADR
2-0
) with the 18 most significant
bits of the output buffer. The result is
stored back into the output buffer.
The complete operation takes only one
clock cycle. The eight least significant
bits of the output buffer are lost.
The Zero multiplexer is controlled by
the SHADD input signal. This allows
selection of either the 18 most signifi-
cant bits of the output buffer or all
zeros for the adder input. When
SHADD is LOW, all zeros will be
selected. When SHADD is HIGH, the
18 most significant bits of the output
buffer are selected enabling the shift-
and-add operation. SHADD is
latched and delayed internally by one
clock cycle.
The output multiplexer is also con-
trolled by the SHADD input signal.
This allows selection of either a filter
cell accumulator, selected by ADR
2-0
,
or the output buffer to be output to
the SUM
25-0
bus. Only the 26 least
significant bits from either a filter cell
accumulator or the output buffer are
output on SUM
25-0
. If SHADD is
LOW during two consecutive clock
cycles (low during the current and
previous clock cycle), the output
multiplexer selects the contents of a
filter cell accumulator addressed by
ADR
2-0
. Otherwise, the output
multiplexer selects the contents of the
output buffer.
If the same address remains on the
ADR
2-0
inputs for more than one clock
cycle, SUM
25-0
will not change to
reflect any updates to the addressed
cell accumulator. Only the result from
the first selection of the cell (first clock
cycle) will be output. This allows the
interface of slow memory devices
where the output needs to be active
for more than one clock cycle. Normal
FIR operation is not affected because
ADR
2-0
is changed sequentially.
NUMBER SYSTEMS
Data and coefficients can be repre-
sented as either 8-bit unsigned or 9-bit
two's complement numbers. All
values are represented as 9-bit two's
complement numbers internally. If
the most significant or sign bit is a
zero, the multiplier can multiply 8-bit
unsigned numbers.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
registers. All timing specifications are
referenced to the rising edge of CLK.
Inputs
DIN
8-0
— Data Input
9-bit data is latched into the X register
of each filter cell simultaneously. The
DIENB signal enables loading of the
data.
CIN
8-0
— Coefficient Input
9-bit coefficients are latched into the C
register of Filter Cell 0. The CIENB
signal enables loading of the coeffi-
cients.
Outputs
SUM
25-0
— Data Output
The 26-bit result from an individual
filter cell will appear when ADR
2-0
is
used to select the filter cell result.
SHADD in conjunction with ADR
2-0
is
used to select the output from the
shift-and-add output stage.
COUT
8-0
— Coefficient Output
The 9-bit coefficient output from
Filter Cell 7 can be connected to the
CIN
8-0
coefficient input of the same
LF43891 to recirculate the coefficients.
COUT
8-0
can also be connected to the
CIN
8-0
of another LF43891 to cascade
the devices. The COENB signal
enables the output of the coefficients.
DCM1
DCM0
Decimation Function
0
0
Decimation registers not used
0
1
One decimation register used (decimation by one-half)
1
0
Two decimation registers used (decimation by one-third)
1
1
Three decimation registers used (decimation by one-fourth)
T
ABLE
1.
D
ECIMATION
M
ODE
S
ELECTION
ERASE
RESET
Clearing Effect
0
0
All accumulators and all registers are cleared
0
1
Only the accumulator addressed by ADR2-0 is cleared
1
0
All registers are cleared (accumulators are not cleared)
1
1
No clearing occurs, internal state remains the same
T
ABLE
2.
R
EGISTER
AND
A
CCUMULATOR
C
LEARING
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