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参数资料
型号： LFEC1E-3TN144C
厂商： Lattice Semiconductor Corporation
文件页数： 78/163页
文件大小： 0K
描述： IC FPGA 1.5KLUTS 97I/O 144-TQFP
标准包装： 60
系列： EC
逻辑元件/单元数： 1500
RAM 位总计： 18432
输入/输出数： 97
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 144-LQFP
供应商设备封装： 144-TQFP（20x20）
其它名称： 220-1770
LFEC1E-3TN144C-ND
2-18
Architecture
LatticeECP/EC Family Data Sheet
MULTADDSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows
the MULTADDSUM sysDSP element.
Figure 2-22. MULTADDSUM
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Multiplier
Add/Sub0
x
n
m
m+n
(default)
m+n
(default)
m+n+1
m+n+2
m+n+1
m+n
(default)
m+n
(default)
m
n
m
n
m
n
m
x
n
m
n
m
Multiplier
Add/Sub1
x
n
m
n
m
n
m
n
m
x
n
m
n
m
n
m
SUM
Multiplier B0
Multiplicand A0
Multiplier B1
Multiplicand A1
Multiplier B2
Multiplicand A2
Multiplier B3
Multiplicand A3
Signed
Shift Register B In
Output
Addn0
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
To Add/Sub0
To Add/Sub0, Add/Sub1
Pipeline
Register
Pipeline
Register
Input
Register
To Add/Sub1
Addn1
Pipeline
Register
Pipeline
Register
Pipeline
Register
Shift Register A In
Shift Register B Out
Shift Register A Out
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register B
Input Data
Register B
Input Data
Register B
Input Data
Register B
Output
Register
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相关代理商/技术参数
参数描述
LFEC1E-3TN144I 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs 97 I/O 1.2V -3 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-4F256C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC1E-4F256I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC1E-4F484C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC1E-4F484I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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