参数资料
型号: LFECP10E-5QN208C
厂商: Lattice Semiconductor Corporation
文件页数: 113/163页
文件大小: 0K
描述: IC FPGA 10.2KLUTS 147I/O 208QFP
标准包装: 24
系列: ECP
逻辑元件/单元数: 10200
RAM 位总计: 282624
输入/输出数: 147
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
3-17
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
tSUCE_EBR
Clock Enable Setup Time to EBR Output
Register
0.18
0.21
0.25
ns
tHCE_EBR
Clock Enable Hold Time to EBR Output Register
-0.14
-0.17
-0.20
ns
tRSTO_EBR
Reset To Output Delay Time from EBR Output
Register
1.47
1.76
2.05
ns
PLL Parameters
tRSTREC
Reset Recovery to Rising Clock
1.00
1.00
1.00
ns
tRSTSU
Reset Signal Setup Time
1.00
1.00
1.00
ns
DSP Block Timing2, 3
tSUI_DSP
Input Register Setup Time
-0.38
-0.30
-0.23
ns
tHI_DSP
Input Register Hold Time
0.71
0.86
1.00
ns
tSUP_DSP
Pipeline Register Setup Time
3.31
3.98
4.64
ns
tHP_DSP
Pipeline Register Hold Time
0.71
0.86
1.00
ns
tSUO_DSP
4
Output Register Setup Time
5.54
6.64
7.75
ns
tHO_DSP
4
Output Register Hold Time
0.71
0.86
1.00
ns
tCOI_DSP
4
Input Register Clock to Output Time
7.50
9.00
10.50
ns
tCOP_DSP
4
Pipeline Register Clock to Output Time
4.66
5.60
6.53
ns
tCOO_DSP
Output Register Clock to Output Time
1.47
1.77
2.06
ns
tSUADSUB
AdSub Input Register Setup Time
-0.38
-0.30
-0.23
ns
tHADSUB
AdSub Input Register Hold Time
0.71
0.86
1.00
ns
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode.
4. These parameters include the Adder Subtractor block in the path.
Timing v.G 0.30
LatticeECP/EC Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
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