参数资料
型号: LM10010SD
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PDSO10
封装: 3 X 3 MM, 0.50 MM PITCH, LLP-10
文件页数: 6/12页
文件大小: 308K
代理商: LM10010SD
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VDD, EN, IDAC_OUT
-0.3V to 6V
VIDA, VIDB, VIDC, VIDS
-0.3V to 6V
ESD Rating (Note 2)
Human Body Model
2 kV
Storage Temperature
-65°C to +150°C
Junction Temperature
+150°C
Operating Ratings
VDD
3.0V to 5.5V
IDAC_OUT
-0.3V to VDD-1.75V
VIDA, VIDB, VIDC, VIDS
-0.3V to 5.5V
EN
-0.3V to 5.5V
Junction Temperature
40°C to +125°C
Ambient Temperature
40°C to +125°C
LLP-10 Thermal Resistance (
θ
JA)
40°C/W
Electrical Characteristics Limits in standard type are for T
J = 25°C only. Limits appearing in boldface type apply
over the full operating junction temperature range (-40°C < T
J < +125°C). Unless otherwise noted, specifications apply to the Typical
Application Circuit. See (Note 4).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply, UVLO, and Enable
I
Q
Quiescent current
VDD=5.0V, V
EN=2.0V
250
280
A
VDD=5.0V, V
EN=2.0V, IFS
340
A
VDD=5.0V, V
EN=0.0V
45
70
A
UVLO
Under voltage rising threshold
2.65
2.95
V
Under voltage falling threshold
2.2
2.45
V
Hysteresis
100
200
300
mV
V
EN
Enable rising threshold
1.20
1.34
1.45
V
Enable hysteresis
50
100
180
mV
I
EN
Enable pullup current
2
A
IDAC
ACC
Accuracy
Measured at full scale
-3
3
%
LSB
DAC step size
I
FS /(2
6
-1)
940
nA
Default
Output code
At startup
46d
Code
Output current
At startup
16
A
I
FS
Full-scale output current
VID[5:0] = 000000b
59.2
A
INL
Integral non-linearity
-1
0.15
1
LSB
DNL
Differential non-linearity
-0.25
0.06
0.25
LSB
Offset
Offset current
VID[5:0] = 111111b
60
nA
V
OUT_MAX
Output compliance
VDD-V
IDAC_OUT, VDD=3V
1.3
1.75
V
VID Logic Inputs
V
IL
Input voltage low
0.4
V
IH
Input voltage high
1.1
V
I
IL
Input current low
-5
A
I
IH
Input current high
5
A
t
DEGLITCH
Input deglitch time
3.4
s
t
1
Input delay time
VIDS rising edge
1
s
t
2
Input hold time VIDA, VIDB, VIDC valid VIDS falling edge
20
s
t
3
Input delay time
VIDS falling edge
1
s
t
4
Input hold time VIDA, VIDB, VIDC valid VIDS rising edge
20
s
t
5
Delay to beginning of IDAC_OUT
transition
Measured from VIDS rising edge
10
17
s
t
6
IDAC_OUT transition time
Time constant for exponential rise
40
s
3
www.national.com
LM10010
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