
30156811
FIGURE 3. Output voltage is controlled via current injection into the feedback node
CURRENT DAC
The LM10010 current DAC is based on a low voltage bandgap
reference setting a current through a precision adjustable re-
sistor. This bandgap is trimmed for precision and gives ex-
cellent performance over temperature. The output current has
a maximum full-scale range of 59.2 A and is adjustable with
the 6-bit VID word. This allows for 64 settings, with a resolu-
tion of 940 nA. The current DAC also has a slew limit to
prevent abrupt changes in the output. As the VID data lines
are set for the output voltage for the regulator, deglitch filters
provide a small delay and the output current rises with a 1-e-
t
function that can be identified by a time constant.
VID PROGRAMMING
Four pins are used to communicate with the LM10010. VIDC,
VIDB, and VIDA are data lines, while VIDS is a latching strobe
that programs in the LM10010 data. As shown in the Timing
Diagram in Figure 1, the falling edge of VIDS latches in the
data from VIDC, VIDB, and VIDA as the lower three LSB of
the IDAC value. After a minimum hold time, the rising edge of
VIDS latches in the data from VIDC, VIDB, and VIDA as the
upper three LSB of the IDAC value. Internally, a delay on
VIDS allows for the setting of all VID lines simultaneously.
The VID data word is set so that the lowest output current is
seen at the highest VID data word (59.2 A at a code of 0d).
Conversely, the lowest current is seen at the highest VID data
word (0 A at 63d). During VID operation with the regulator,
this will translate to the lowest output voltage with the lowest
VID word, and the highest output voltage with the highest VID
word. The communications pins can be used with a low volt-
age microcontroller, with a maximum V
IL of 0.4V and a mini-
mum V
IH of 1.1V.
Upon startup, the IDAC is set at a code of 46d, which trans-
lates to approximately 16 A. This default startup value is
trimmed at final test. For applications with a different default
output current at startup, please contact National Semicon-
ductor.
DEGLITCH TIME
The four digital input pins all have deglitch filters which pre-
vent transient noise from affecting the operation of the
LM10010. These filters will also impart a small delay to the
digital signal. On the VIDS latching signal, there is an addi-
tional delay. As mentioned previously, this allows for the VID
data lines and the VIDS strobe to be set simultaneously with-
out the need for setup time.
ENABLE PIN AND UVLO
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.34V (typical). The EN pin has 100 mV of
hysteresis and will disable the output when the enable voltage
falls below 1.24V (typical). If EN is not used, it can be left
open, and will be pulled high by an internal 2 A current
source. Since the enable pin has a precise turn-on threshold
it can be used along with an external resistor divider network
from VIN to configure the device to turn-on at a precise input
voltage.
The LM10010 has a built-in under-voltage lockout (UVLO)
protection circuit that keeps the device from operating until
the input voltage reaches 2.65V (typical). The UVLO thresh-
old has 200 mV of hysteresis that keeps the device from
responding to power-on glitches during startup. Note that the
enable and the UVLO are functionally the same as a reset.
Bringing the device back from a low enable setting or from a
VDD under-voltage event will reset the device back to its
startup default setting.
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LM10010