2.0 Internal User-Programmable Registers
(Continued)
Bits 12–15
are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the ac-
quisition mode for a fixed number of clock cycles (nine clock
cycles, for 12-bit + sign conversions and two clock cycles for
8-bit + sign conversions or “watchdog” comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9 +
2D) clock cycles for 12-bit + sign conversions and (2 + 2D)
clock cycles for 8-bit + sign conversions or “watchdog” com-
parisons, where D is the value stored in Bits 12–15. The
minimum acquisition time compensates for the typical inter-
nal multiplexer series resistance of 2 k
, and any additional
delay created by Bits 12–15 compensates for source resis-
tances greater than 80
. (For this acquisition time discus-
sion, numbers in ( ) are shown for the LM12L458 operating
at 6 MHz. The necessary acquisition time is determined by
the source impedance at the multiplexer input. If the source
resistance (R
S
)
<
80
and the clock frequency is 6 MHz, the
value stored in bits 12–15 (D) can be 0000. If R
>
80
, the
following equations determine the value that should be
stored in bits 12–15.
D = 0.45 x R
S
x f
CLK
for 12-bits + sign
D = 0.36 x R
S
x f
CLK
for 8-bits + sign and “watchdog”
R
is in k
and f
is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12L458’s multiplexer in-
puts.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
A4 A3 A2 A1 A0
0
0
to
1
0
0
to
1
0
0
to
1
0
0
to
1
0
0
to
1
0
0
to
1
1
0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
0
0
(Instruction RAM
V
IN
V
IN+
0
R/W
Pause
Loop
1
0
1
0
Watch-
dog
1
R/W
Acquisition Time
8/12
Timer
Sync
1
0
1
0
(Instruction RAM
0
R/W
Comparison Limit
#
1
1
0
1
0
1
R/W
Don’t Care
>
/
<
Sign
1
0
1
0
(Instruction RAM
0
R/W
Comparison Limit
#
2
1
0
1
0
1
R/W
Don’t Care
>
/
<
Sign
1
0
1
0
0
Configuration
Register
R/W
I/O
Sel
Auto
Zero
ec
Chan
Mask
Stand-
by
Full
Cal
Auto-
Zero
Test
= 0
Reset
Start
1
0
0
0
1
R/W
Don’t Care
DIAG
RAM Pointer
1
0
0
1
0
Interrupt Enable
Register
R/W
INT7
Don’t
Care
INT5
INT4
INT3
INT2
INT1
INT0
1
0
0
1
1
R/W
Number of Conversions in Conversion
FIFO to Generate INT2
“0”
INST5
Sequencer Address to
Generate INT1
INST2
INST1
Address of Sequencer
Instruction
being Executed
1
1
0
0
1
1
0
0
0
1
Interrupt Status
Register
R
R
INST7
INST4
INST3
INST0
Actual Number of Conversions Results in Conversion
FIFO
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Timer
Register
R/W
R/W
R
R
R
R
Timer Preset: Low Byte
Timer Preset: High Byte
Conversion Data: LSBs
Sign
Limit
#
1 Status
Limit
#
2 Status
Conversion
FIFO
Address or Sign
Conversion Data: MSBs
Limit Status
Register
FIGURE 14. LM12L458 Memory Map for 8-Bit Wide Databus (BW = “1” and Test Bit = “0”)
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