Application Information (Continued)
POT LADDER ARCHITECTURE
The Pot contains a chain of R1/R2 resistor dividers in a lad-
der form, as shown in
Figure 4. Each R1 is actually a series
of 8 resistors, with a CMOS switch that taps into the resistor
chain according to the attenuation level chosen. For any
given attenuation setting, there is only one CMOS switch
closed (no paralleling of ladders). The input impedance
therefore remains constant, while the output impedance
changes as the attenuation level changes. It is important to
note that the architecture is a series of resistor dividers, and
not a straight, tapped resistor, so the Pot is not a variable
resistor; it is a variable voltage divider.
ATTENUATION STEP SCHEME
The fundamental attenuation step scheme for the LM1971 is
shown in
Figure 5. It is also possible to obtain any integer
value attenuation step through programming, in addition to
the 2 dB and 4 dB steps shown in
Figure 5. All higher attenu-
ation step schemes can have clickless and popless perfor-
mance. Although it is possible to “skip” attenuation points by
not sending all of the data, clickless and popless perfor-
mance will suffer. It is highly recommended that all of the
data points should be sent for each attenuation level. This
ensures flawless operation and performance when making
steps larger than 1 dB.
INPUT IMPEDANCE
The input impedance of a Pot is constant at a nominal
40 k
. Since the LM1971 is a single-supply operating de-
vice, it is necessary to have both input and output coupling
caps as shown in
Figure 1. To ensure full low-frequency re-
sponse,a1F coupling cap should be used.
OUTPUT IMPEDANCE
The output impedance of a Pot varies typically between
25 k
and 35 k and changes nonlinearly with step
changes. Since a Pot is made up of a resistor ladder net-
work with logarithmic attenuation, the output impedance is
nonlinear. Due to this configuration, a Pot cannot be con-
sidered as a linear potentiometer; it is a logarithmic attenua-
tor.
The linearity of a Pot cannot be measured directly without a
buffer because the input impedance of most measurement
systems is not high enough to provide the required accuracy.
The lower impedance of the measurement system would
load down the output and an incorrect reading would result.
To prevent loading, a JFET input op amp should be used as
the buffer/amplifier.
OUTPUT BUFFERING
There are two performance issues to be aware of that are re-
lated to a Pot’s output stage. The first concern is to prevent
audible clicks with attenuation changes, while the second is
to prevent loading and subsequent linearity errors. The out-
put stage of a Pot needs to be buffered with a low input bias
DS012353-4
FIGURE 3. Serial Data Format Transfer Process
DS012353-5
FIGURE 4. Resistor Ladder Architecture
LM 1971 Channel Attenuation
vs Digital Step Value
(1 dB, 2 dB, and 4 dB Steps)
DS012353-6
FIGURE 5. LM1971 Attenuation Step Scheme
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