ting the resistor from the ILIM pin to GND (R
ILIM) to the
appropriate value to allow the maximum ripple current,
ΔI
LMAX plus the DC output current through the high-side FET
during normal operation. The maximum ripple current can be
described as:
where V
INMAX, VINMIN, VOUTMAX, VOUTMIN, LMIN and FSWMIN are
the respective maximum and minimum conditions of the sys-
tem as defined by the component tolerance and device vari-
ation. From this, the maximum allowable current through the
high-side FET (I
HSMAX) of device can be described as:
where I
OUTMAX is the maximum defined DC output current, up
to 15 A. Once the I
HSMAX value has been determined, a nom-
inal value of the R
ILIMresistor can be calculated as follows:
where the R
ILIMvalue is the nominal resistance necessary for
the given I
HSMAX value. A conservative design should also
take into account the device variation over V
IN and tempera-
ture, as seen seen in the Electrical Characteristics table for
the I
CLR parameter and the typical performance characteris-
tics. These variations can cause the I
HSMAX value to increase,
depending on the range of the input voltage and junction tem-
perature.
CONTROL LOOP COMPENSATION
The LM21215 incorporates a high bandwidth amplifier be-
tween the FB and COMP pins to allow the user to design a
compensation network that matches the application. This
section will walk through the various steps in obtaining the
open loop transfer function.
There are three main blocks of a voltage mode buck switcher
that the power supply designer must consider when designing
the control system; the power train, modulator, and the com-
pensated error amplifier. A closed loop diagram is shown in
30103712
FIGURE 8. Loop Diagram
The power train consists of the output inductor (L) with DCR
(DC resistance R
DCR), output capacitor (C0) with ESR (effec-
tive series resistance R
ESR), and load resistance (Ro). The
error amplifier (EA) constantly forces FB to 0.6V. The passive
compensation components around the error amplifier help
maintain system stability. The modulator creates the duty cy-
cle by comparing the error amplifier signal with an internally
generated ramp set at the switching frequency.
There are three transfer functions that must be taken into
consideration when obtaining the total open loop transfer
function; COMP to SW (Modulator) , SW to V
OUT (Power
Train), and V
OUT to COMP (Error Amplifier). The COMP to SW
transfer function is simply the gain of the PWM modulator.
where
ΔV
RAMP is the oscillator peak-to-peak ramp voltage
(nominally 0.8 V). The SW to COMP transfer function includes
the output inductor, output capacitor, and output load resis-
tance. The inductor and capacitor create two complex poles
at a frequency described by:
In addition to two complex poles, a left half plane zero is cre-
ated by the output capacitor ESR located at a frequency
described by:
A Bode plot showing the power train response can be seen
below.
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LM21215