参数资料
型号: LM22678QTJ-5.0
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 8.75 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PSSO7
封装: PLASTIC, TO-263, 7 PIN
文件页数: 15/16页
文件大小: 535K
代理商: LM22678QTJ-5.0
30076150
FIGURE 2. Output Current in Foldback vs.
Nominal Duty Cycle
The percentage of output current limit fold back is affected by
duty
cycle,
inductance,
and
switching
frequency.
See Figure 2 for details.
The current limit will only protect the inductor from a runaway
condition if the LM22678 is operating in its safe operating
area. A runaway condition of the inductor is potentially catas-
trophic to the application. For every design, the safe operating
area needs to be calculated. Factors in determining the safe
operating area are the switching frequency, input voltage,
output voltage, minimum on-time and feedback voltage dur-
ing an over current condition.
As a first pass check, if the following equation holds true, a
given design is considered in a safe operating area and the
current limit will protect the circuit:
V
IN x TBLK x F < VOUT x 0.724
If the equation above does not hold true, the following sec-
ondary equation will need to hold true to be in safe operating
area:
If both equations do not hold true, a particular design will not
have an effective current limit function which might damage
the circuit during startup, over current conditions, or steady
state over current and short circuit condition. Oftentimes a
reduction of the maximum input voltage will bring a design into
the safe operating area.
Soft-Start
The soft-start feature allows the regulator to gradually reach
the initial steady state operating point, thus reducing start-up
stresses and surges. The soft-start is fixed to 500 s (typical)
start-up time and cannot be modified.
Boot Pin
The LM22678 integrates an N-Channel FET switch and as-
sociated floating high voltage level shift / gate driver. This gate
driver circuit works in conjunction with an internal diode and
an external bootstrap capacitor. A 0.01 F ceramic capacitor
connected with short traces between the BOOT pin and the
SW pin is recommended to effectively drive the internal FET
switch. During the off-time of the switch, the SW voltage is
approximately -0.5V and the external bootstrap capacitor is
charged from the internal supply through the internal boot-
strap diode. When operating with a high PWM duty-cycle, the
buck switch will be forced off each cycle to ensure that the
bootstrap capacitor is recharged. See the maximum duty-cy-
cle section for more details.
Thermal Protection
Internal Thermal Shutdown circuitry protects the LM22678 in
the event the maximum junction temperature is exceeded.
When activated, typically at 150°C, the regulator is forced into
a low power reset state. There is a typical hysteresis of 15
degrees.
Internal Compensation
The LM22678 has internal compensation designed for a sta-
ble loop with a wide range of external power stage compo-
nents.
Insuring stability of a design with a specific power stage (in-
ductor and output capacitor) can be tricky. The LM22678
stability can be verified over varying loads and input and out-
put voltages using WEBENCH Designer online circuit sim-
ulation tool at www.national.com. A quick start spreadsheet
can also be downloaded from the online product folder.
The internal compensation of the -ADJ option of the LM22678
is optimized for output voltages below 5V. If an output voltage
of 5V or higher is needed, the -5.0 option with an additional
external resistor divider may also be used.
The typical location of the internal compensation poles and
zeros as well as the DC gain is given in Table 1. The LM22678
has internal type III compensation allowing for the use of most
output capacitors including ceramics.
This information can be used to calculate the transfer function
from the FB pin to the internal compensation node (input to
the PWM comparator in the block diagram).
TABLE 1.
Corners
Frequency
Pole 1
150 kHz
Pole 2
250 kHz
Pole 3
100 Hz
Zero 1
1.5 kHz
Zero 2
15 kHz
DC gain
37.5 dB
For the power stage transfer function the standard voltage
mode formulas for the double pole and the ESR zero apply:
The peak ramp level of the oscillator signal feeding into the
PWM comparator is V
IN/10 which equals a gain of 20dB of
this modulator stage of the IC. The -5.0 fixed output voltage
option has twice the gain of the compensation transfer func-
tion compared to the -ADJ option which is 43.5dB instead of
37.5dB.
Generally, calculation as well as simulation can only aid in
selecting good power stage components. A good design prac-
tice is to test for stability with load transient tests or loop
measurement tests. Application note AN-1889 shows how to
www.national.com
8
LM22678/LM22678Q
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