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参数资料
| 型号： | LM2540-9ERD6H |
| 厂商： | POWER-ONE INC |
| 元件分类： | 电源模块 |
| 英文描述： | 2-OUTPUT 50 W AC-DC REG PWR SUPPLY MODULE |
| 封装： | METAL, CASE M02, MODULE |
| 文件页数： | 15/24页 |
| 文件大小： | 982K |
| 代理商： | LM2540-9ERD6H |
Cassette Style
AC-DC Converters
M Series
Edition 5/5.2000
22/24
V ACFAIL signal (VME)
Available for units with
Uo1 = 5.1 V
This option defines an undervoltage monitoring circuit for
the input or the input and main output voltage equivalent to
option D and generates the ACFAIL signal (V signal) which
conforms to the VME standard.
The low state level of the ACFAIL signal is specified at a
sink current of
IV = 48 mA to UV ≤ 0.6 V (open-collector out-
put of a NPN transistor). The pull-up resistor feeding the
open-collector output should be placed on the VME back-
plane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time
th of at least 4 ms before the 5.1 V
output drops to 4.875 V when the 5.1 V output is fully
loaded. This hold-up time
th is provided by the internal input
capacitance. Consequently the working input voltage and
the threshold level
Ut should be adequately above the mini-
mum input voltage
Ui min of the converter so that enough
energy is remaining in the input capacitance.
Formula for threshold level for desired value of
th:
2
Po (th + 0.3 ms) 100
Uti =
––––––––––––––––––––– +
Ui min2
Ci min
η
If the input voltage is below the required level, an external
hold-up capacitor (
Ci ext) should be added. If the units are
AC powered, an external input capacitor cannot be applied
unless an additional rectifier is provided.
Formula for additional external input capacitor
2
Po (th + 0.3 ms) 100
Ci ext = ––––––––––––––––––––– – Ci min
η (U
ti
2 – Ui min2)
whereas:
Ci min = minimum internal input capacitance [mF], accord-
ing to the table below
Ci ext = external input capacitance [mF]
Po
= output power [W]
η
= efficiency [%]
th
= hold-up time [ms]
Ui min = minimum input voltage [V]
Ut
= threshold level [V]
The threshold level
Uti of option V2 and V3 is adjusted dur-
ing manufacture to a value according to the table below.
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 5 as soon as one of the monitored voltages drops below
the preselected threshold level
Ut. The return for this signal
is Vo1– (pin 23). The V output recovers when the monitored
voltage(s) exceed(s)
Ut + Uh. The threshold level Ut is either
adjustable by a potentiometer, accessible through a hole in
the front cover, or is factory adjusted to a determined cus-
tomer specified value.
Versions V0, V2 and V3 are available as shown below.
Table 23: Available internal input capacitance and factory
potentiometer setting of Uti with resulting hold-up time
Types
LM/LMZ
Unit
Ci min
0.14
mF
Uti
120
V DC
th
8.18
ms
Table 24: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment range
Typical hysteresis
Uh [% of Ut]
(VME compatible)
Ui
Uo1
of threshold level
Ut
for
Ut min...Ut max
Uti
Uto
Uhi
Uho
V2
yes
no
Ui min...Ui max 1
–
3.0...0.5
-
V3
yes
Ui min...Ui max 1
0.95...0.98
Uo1 2
3.0...0.5
"0"
V0
yes
no
Ui min...Ui max 3 4
-
2.2...0.4
-
yes
Ui min...Ui max 3 4
0.95...0.98
Uo1 2
2.2...0.4
"0"
1 Threshold level adjustable by potentiometer (not recommended for mobile applications).
2 Fixed value between 95% and 98% of Uo1 (tracking), output undervoltage monitoring is not a requirement of VME standard.
3 Adjusted at Io nom
4 Fixed value, resistor-adjusted (
±2% at 25°C) acc. to customer's specifications; individual type number is determined by Power-One
Vo1+
Vo1–
V
UV
IV
Rp
Input
11009
V output (V0, V2, V3):
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1.
UV
≤ 0.6 V (logic low) corre-
sponds to a monitored voltage level (
Ui and/or Uo1)
< U
t.
The current
IV through the open collector should not exceed
50 mA. The NPN output is not protected against external
overvoltages.
UV should not exceed 80 V.
Ui, Uo1 status
V output,
UV
Ui or Uo1 < Ut
low, L,
UV ≤ 0.6 V at IV = 50 mA
Ui and Uo1 > Ut + Uh
high, H,
IV ≤ 25 A at UV = 5.1 V
Fig. 28
Output configuration of options V0, V2 and V3
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