参数资料
型号: LM25575Q0MH
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PDSO16
封装: TSSOP-16
文件页数: 2/22页
文件大小: 401K
代理商: LM25575Q0MH
Shutdown / Standby
The LM25575Q0 contains a dual level Shutdown (SD) circuit.
When the SD pin voltage is below 0.7V, the regulator is in a
low current shutdown mode. When the SD pin voltage is
greater than 0.7V but less than 1.225V, the regulator is in
standby mode. In standby mode the Vcc regulator is active
but the output switch is disabled. When the SD pin voltage
exceeds 1.225V, the output switch is enabled and normal op-
eration begins. An internal 5A pull-up current source config-
ures the regulator to be fully operational if the SD pin is left
open.
An external set-point voltage divider from VIN to GND can be
used to set the operational input range of the regulator. The
divider must be designed such that the voltage at the SD pin
will be greater than 1.225V when Vin is in the desired oper-
ating range. The internal 5A pull-up current source must be
included in calculations of the external set-point divider. Hys-
teresis of 0.1V is included for both the shutdown and standby
thresholds. The SD pin is internally clamped with a 1k
re-
sistor and an 8V zener clamp. The voltage at the SD pin
should never exceed 14V. If the voltage at the SD pin exceeds
8V, the bias current will increase at a rate of 1 mA/V.
The SD pin can also be used to implement various remote
enable / disable functions. Pulling the SD pin below the 0.7V
threshold totally disables the controller. If the SD pin voltage
is above 1.225V the regulator will be operational.
Oscillator and Sync Capability
The LM25575Q0 oscillator frequency is set by a single exter-
nal resistor connected between the RT pin and the AGND pin.
The R
T resistor should be located very close to the device and
connected directly to the pins of the IC (RT and AGND).To
set a desired oscillator frequency (F), the necessary value for
the R
T resistor can be calculated from the following equation:
The SYNC pin can be used to synchronize the internal oscil-
lator to an external clock. The external clock must be of
higher frequency
than the free-running frequency set by the
R
T resistor. A clock circuit with an open drain output is the
recommended interface from the external clock to the SYNC
pin. The clock pulse duration should be greater than 15ns.
30071105
FIGURE 3. Sync from External Clock
30071106
FIGURE 4. Sync from Multiple Devices
Multiple LM25575Q0 devices can be synchronized together
simply by connecting the SYNC pins together. In this config-
uration all of the devices will be synchronized to the highest
frequency device. The diagram in Figure 5 illustrates the
SYNC input/output features of the LM25575Q0. The internal
oscillator circuit drives the SYNC pin with a strong pull-down /
weak pull-up inverter. When the SYNC pin is pulled low either
by the internal oscillator or an external clock, the ramp cycle
of the oscillator is terminated and a new oscillator cycle be-
gins. Thus, if the SYNC pins of several LM25575Q0 IC’s are
connected together, the IC with the highest internal clock fre-
quency will pull the connected SYNC pins low first and termi-
nate the oscillator ramp cycles of the other IC’s. The
LM25575Q0 with the highest programmed clock frequency
will serve as the master and control the switching frequency
of the all the devices with lower oscillator frequency.
www.national.com
10
LM25575Q0
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