参数资料
型号: LM27402SQ
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 1350 kHz SWITCHING FREQ-MAX, QCC16
封装: 4 X 4 MM, 0.80 MM HEIGHT, 0.65 MM PITCH, LLP-16
文件页数: 7/32页
文件大小: 653K
代理商: LM27402SQ
width, a good approximation of the output voltage deviation
is:
ΔV
TR (V) is the transient output voltage deviation, ΔIOUT (A)
is the load current step change and L (H) is the filter induc-
tance. V
L is the minimum inductor voltage which is duty ratio
dependent.
V
L = VOUT , if D 0.5,
V
L = VIN - VOUT , if D > 0.5
For a desired
ΔV
TR (V), a minimum output capacitance can
be found by:
INPUT CAPACITOR SELECTION (C
IN)
Input capacitors are necessary to limit the input ripple voltage
while supplying much of the switch current during the high-
side FET on-time. It is generally recommended to use ceramic
capacitors at the input as they provide both a low impedance
and a high RMS current rating. It is important to choose a
stable dielectric for the ceramic capacitor such as X5R or
X7R. A quality dielectric provides better temperature perfor-
mance and also avoids the DC voltage derating inherent with
Y5V capacitors. The input capacitor should be placed as
close as possible to the drain of the high-side FET and the
source of the low-side FET. Non-ceramic input capacitors
should be selected for RMS current rating, minimum ripple
voltage, and to provide damping. A good approximation for
the required ripple current rating is given by the relationship:
The highest requirement for RMS current rating occurs for D
= 0.5. When D = 0.5, the RMS ripple current rating of the input
capacitor should be greater than half the output current. Low
ESR ceramic capacitors can be placed in parallel with higher
valued bulk capacitors to provide optimized input filtering for
the regulator.
The input voltage ripple can be calculated using:
The minimum amount of input capacitance as a function of
desired input voltage ripple can be calculated using:
USING PRECISION ENABLE
If enable (EN) is not controlled directly, the LM27402 can be
pre-programmed to turn on at an input voltage higher than the
UVLO voltage. This can be done with an external resistor di-
vider from VIN to EN and EN to GND as shown in Figure 6.
30092612
FIGURE 6. Enable Sequencing
The resistor values of R
A and RB can be relatively sized to
allow the EN pin to reach the enable threshold voltage (1.17V)
at the appropriate input supply voltage. With the enable cur-
rent source considered, the equation to solve for R
A is:
where R
A is the resistor from VIN to EN, RB is the resistor from
EN to GND, I
EN is the internal enable pull-up current (2A)
and 1.17V is the fixed precision enable threshold voltage.
Typical values for R
B range from 10k to 100k.
SETTING THE SOFT-START TIME
Adding a soft-start capacitor can reduce inrush currents and
provide a monotonic startup. The size of the soft-start capac-
itor can be calculated by:
The size of the C
SS capacitor is influenced by the desired soft-
start time t
ss (s) , the soft-start current Iss (A) (3 A) and the
nominal feedback (FB) voltage level of 0.6V. If V
VIN and
V
VDD are above the UVLO voltage level (2.90V) and EN is
above the enable threshold (1.17V), the soft-start sequence
will begin. The LM27402 defaults to a minimum startup time
of 1.28 ms when no soft-start capacitor is connected. In other
words, the LM27402 will not startup faster than 1.28 ms. The
soft-start capacitor is discharged when enable is cycled, dur-
ing UVLO, OTP, or when the LM27402 enters hiccup mode
from an over-current event.
There is a delay between EN transitioning above 1.17V and
the beginning of the soft-start sequence. The delay allows the
LM27402 to initialize its internal circuitry. Once the output has
charged to 94% of the nominal output voltage and SS/TRACK
has exceeded 564 mV, the PGOOD indicator will transition
high as illustrated in Figure 7.
15
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LM27402
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