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参数资料
| 型号： | LM2742 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages |
| 中文描述： | N沟道场效应管同步降压稳压控制器输出电压低 |
| 文件页数： | 2/22页 |
| 文件大小： | 619K |
| 代理商： | LM2742 |
Application Information (Continued)
MOSFET GATE DRIVERS
The LM2742 has two gate drivers designed for driving
N-channel MOSFETs in a synchronous mode. Power for the
drivers is supplied through the BOOT pin. For the high side
gate (HG) to fully turn on the top FET, the BOOT voltage
must be at least one V
GS(th) greater than Vin. (BOOT
≥
2*Vin) This voltage can be supplied by a separate, higher
voltage source, or supplied from a local charge pump struc-
ture. In a system such as a desktop computer, both 5V and
12V are usually available. Hence if Vin was 5V, the 12V
supply could be used for BOOT. 12V is more than 2*Vin, so
the HG would operate correctly. For a BOOT of 12V, the
initial gate charging current is 2A, and the initial gate dis-
charging current is typically 6A.
In a system without a separate, higher voltage, a charge
pump (bootstrap) can be built using a diode and small ca-
pacitor, Figure 1. The capacitor serves to maintain enough
voltage between the top FET gate and source to control the
device even when the top FET is on and its source has risen
up to the input voltage level.
The LM2742 gate drives use a BiCMOS design. Unlike some
other bipolar control ICs, the gate drivers have rail-to-rail
swing, ensuring no spurious turn-on due to capacitive cou-
pling.
POWER GOOD SIGNAL
The power good signal is the or-gated flag representing
over-voltage and under-voltage protection. If the output volt-
age is 18% over it’s nominal value, V
FB = 0.7V, or falls 30%
below that value, V
FB = 0.41V, the power good flag goes low.
It will return to a logic high whenever the feedback pin
voltage is between 70% and 118% of 0.6V. The power good
pin is an open drain output that can be pulled up to logic
voltages of 5V or less with a 10k
resistor.
UVLO
The 4.2V turn-on threshold on V
CC has a built in hysteresis
of 0.6V. Therefore, if V
CC drops below 3.6V, the chip enters
UVLO mode. UVLO consists of turning off the top FET,
turning off the bottom FET, and remaining in that condition
until V
CC rises above 4.2V. As with shutdown, the soft start
capacitor is discharged through a FET, ensuring that the next
start-up will be smooth.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the
low side FET while it is on. The R
DSON of the FET is a known
value, hence the current through the FET can be determined
as:
V
DS =I*RDSON
The current limit is determined by an external resistor, R
CS,
connected between the switch node and the ISEN pin. A
constant current of 50A is forced through Rcs, causing a
fixed voltage drop. This fixed voltage is compared against
V
DS and if the latter is higher, the current limit of the chip has
been reached. R
CS can be found by using the following:
R
CS =RDSON(LOW) * ILIM/50A
For example, a conservative 15A current limit in a 10A
design with a minimum R
DSON of 10m
would require a
3.3k
resistor. Because current sensing is done across the
low side FET, no minimum high side on-time is necessary. In
the current limit mode the LM2742 will turn the high side off
and the keep low side on for as long as necessary. The chip
also discharges the soft start capacitor through a fixed 95A
source. In this way, smooth ramping up of the output voltage
as with a normal soft start is ensured. The output of the
LM2742 internal error amplifier is limited by the voltage on
the soft start capacitor. Hence, discharging the soft start
capacitor reduces the maximum duty cycle D of the control-
ler. During severe current limit, this reduction in duty cycle
will reduce the output voltage, if the current limit conditions
lasts for an extended time.
During the first few nanoseconds after the low side gate
turns on, the low side FET body diode conducts. This causes
an additional 0.7V drop in V
DS. The range of VDS is normally
much lower. For example, if R
DSON were 10m
and the
current through the FET was 10A, V
DS would be 0.1V. The
current limit would see 0.7V as a 70A current and enter
current limit immediately. Hence current limit is masked dur-
ing the time it takes for the high side switch to turn off and the
low side switch to turn on.
SHUT DOWN
If the shutdown pin SD is pulled low, the LM2742 discharges
the soft start capacitor through a MOSFET switch. The high
side and low side switches are turned off. The LM2742
remains in this state until SD is released.
DESIGN CONSIDERATIONS
The following is a design procedure for all the components
needed to create the circuit shown in Figure 3 in the Ex-
ample Circuits section, a 5V in to 1.2V out converter, capable
of delivering 10A with an efficiency of 85%. The switching
frequency is 300kHz. The same procedures can be followed
to create many other designs with varying input voltages,
output voltages, and output currents.
INPUT CAPACITOR
The input capacitors in a Buck switching converter are sub-
jected to high stress due to the input current waveform,
which is a square wave. Hence input caps are selected for
their ripple current capability and their ability to withstand the
heat generated as that ripple current runs through their ESR.
Input rms ripple current is approximately:
20087502
FIGURE 1. BOOT Supplied by Charge Pump
LM2742
www.national.com
10
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