参数资料
型号: LM3151MHE-2.5
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO14
封装: TSSOP-14
文件页数: 20/20页
文件大小: 479K
代理商: LM3151MHE-2.5
Theory of Operation
The LM3151/2/3 synchronous step-down SIMPLE SWITCH-
ER Controller employs a Constant On-Time (COT) archi-
tecture which is a derivative of the hysteretic control scheme.
COT relies on a fixed switch on-time to regulate the output.
The on-time of the high-side switch is set internally by resistor
R
ON. The LM3151/2/3 automatically adjusts the on-time in-
versely with the input voltage to maintain a constant frequen-
cy. Assuming an ideal system and V
IN is much greater than
1V, the following approximations can be made:
The on-time, t
ON:
Where K = 100 pC, and R
ON is specified in the electrical char-
acteristics table.
Control is based on a comparator and the on-timer, with the
output voltage feedback (FB) attenuated and then compared
with an internal reference of 0.6V. If the attenuated FB level
is below the reference, the high-side switch is turned on for a
fixed time, t
ON, which is determined by the input voltage and
the internal resistor, R
ON. Following this on-time, the switch
remains off for a minimum off-time, t
OFF, as specified in the
Electrical Characteristics table or until the attenuated FB volt-
age is less than 0.6V. This switching cycle will continue while
maintaining regulation. During continuous conduction mode
(CCM), the switching frequency depends only on duty cycle
and on-time. The duty cycle can be calculated as:
Where the switching frequency of a COT regulator is:
Typical COT hysteretic controllers need a significant amount
of output capacitor ESR to maintain a minimum amount of
ripple at the FB pin in order to switch properly and maintain
efficient regulation. The LM3151/2/3 however utilizes propri-
etary, Emulated Ripple Mode Control Scheme (ERM) that
allows the use of ceramic output capacitors without additional
equivalent series resistance (ESR) compensation. Not only
does this reduce the need for output capacitor ESR, but also
significantly reduces the amount of output voltage ripple seen
in a typical hysteretic control scheme. The output ripple volt-
age can become so low that it is comparable to voltage-mode
and current-mode control schemes.
Regulation Comparator
The output voltage is sampled through the FB pin and then
divided down by two internal resistors and compared to the
internal reference voltage of 0.6V by the error comparator. In
normal operation, an on-time period is initiated when the sam-
pled output voltage at the input of the error comparator falls
below 0.6V. The high-side switch stays on for the specified
on-time, causing the sampled voltage on the error comparator
input to rise above 0.6V. After the on-time period, the high-
side switch stays off for the greater of the following:
1) Minimum off time as specified in the electrical characteris-
tics table
2) The error comparator sampled voltage falls below 0.6V
Over-Voltage Comparator
The over-voltage comparator is provided to protect the output
from over-voltage conditions due to sudden input line voltage
changes or output loading changes. The over-voltage com-
parator continuously monitors the attenuated FB voltage ver-
sus a 0.72V internal reference. If the voltage at FB rises above
0.72V the on-time pulse is immediately terminated. This con-
dition can occur if the input or the output load changes sud-
denly. Once the over-voltage protection is activated, the HG
and LG signals remain off until the attenuated FB voltage falls
below 0.72V.
Current Limit
Current limit detection occurs during the off-time by monitor-
ing the current through the low-side switch. If during the off-
time the current in the low-side switch exceeds the user
defined current limit value, the next on-time cycle is immedi-
ately terminated. Current sensing is achieved by comparing
the voltage across the low-side switch against an internal ref-
erence value, V
CL, of 200 mV. If the voltage across the low-
side switch exceeds 200 mV, the current limit comparator will
trigger logic to terminate the next on-time cycle. The current
limit I
CL, can be determined as follows:
Where I
OCL is the user-defined average output current limit
value, R
DS(ON)max is the resistance value of the low-side FET
at the expected maximum FET junction temperature, V
CL is
the internal current limit reference voltage and T
j is the junc-
tion temperature of the LM3151/2/3.
Figure 1 illustrates the inductor current waveform. During nor-
mal operation, the output current ripple is dictated by the
switching of the FETs. The current through the low-side
switch, I
valley, is sampled at the end of each switching cycle
and compared to the current limit threshold voltage, V
CL. The
valley current can be calculated as follows:
Where I
OUT is the average output current and ΔIL is the peak-
to-peak inductor ripple current.
If an overload condition occurs, the current through the low-
side switch will increase which will cause the current limit
comparator to trigger the logic to skip the next on-time cycle.
The IC will then try to recover by checking the valley current
during each off-time. If the valley current is greater than or
equal to I
CL, then the IC will keep the low-side FET on and
allow the inductor current to further decay.
Throughout the whole process, regardless of the load current,
the on-time of the controller will stay constant and thereby the
positive ripple current slope will remain constant. During each
on-time the current ramps up an amount equal to:
9
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LM3151/LM3152/LM3153
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