参数资料
型号: LM3402_07
厂商: National Semiconductor Corporation
英文描述: 0.5A Constant Current Buck Regulator for Driving High Power LEDs
中文描述: 0.5A的恒流降压稳压器用于驱动高功率LED
文件页数: 13/24页
文件大小: 431K
代理商: LM3402_07
Schottky diode at 350 mA is approximately 0.65V and the
θ
JA is 88°C/W. Power dissipation and temperature rise can be
calculated as:
P
D = 0.065 x 0.65 = 42 mW
T
RISE = 0.042 x 88 = 4°C
C
B AND CF
The bootstrap capacitor C
B should always be a 10 nF ceramic
capacitor with X7R dielectric. A 25V rating is appropriate for
all application circuits. The linear regulator filter capacitor C
F
should always be a 100 nF ceramic capacitor, also with X7R
dielectric and a 25V rating.
EFFICIENCY
To estimate the electrical efficiency of this example the power
dissipation in each current carrying element can be calculated
and summed. Electrical efficiency,
η, should not be confused
with the optical efficacy of the circuit, which depends upon the
LEDs themselves.
Total output power, P
O, is calculated as:
P
O = IF x VO = 0.361 x 49.2 = 17.76W
Conduction loss, P
C, in the internal MOSFET:
P
C = (IF
2
x R
DSON) x D = (0.361
2
x 1.5) x 0.82 = 160 mW
Gate charging and VCC loss, P
G, in the gate drive and linear
regulator:
P
G = (IIN-OP + fSW x QG) x VIN
P
G = (600 x 10
-6
+ 3 x 105 x 3 x 10-9) x 60 = 90 mW
Switching loss, P
S, in the internal MOSFET:
P
S = 0.5 x VIN x IF x (tR + tF) x fSW
P
S = 0.5 x 60 x 0.361 x 40 x 10
-9
x 3 x 105 = 130 mW
AC rms current loss, P
CIN, in the input capacitor:
P
CIN = IIN(rms)
2
x ESR = (0.134)2 x 0.006 = 0.1 mW (negligible)
DCR loss, P
L, in the inductor
P
L = IF
2
x DCR = 0.352 x 1.1 = 135 mW
Recirculating diode loss, P
D = 42 mW
Current Sense Resistor Loss, P
SNS = 69 mW
Electrical efficiency,
η = P
O / (PO + Sum of all loss terms) =
17.76 / (17.76 + 0.62) = 96%
Temperature Rise in the LM3402HV IC is calculated as:
T
LM3402 = (PC + PG + PS) x θJA = (0.16 + 0.084 + 0.13) x 200
= 74.8°C
Layout Considerations
The performance of any switching converter depends as
much upon the layout of the PCB as the component selection.
The following guidelines will help the user design a circuit with
maximum rejection of outside EMI and minimum generation
of unwanted EMI.
COMPACT LAYOUT
Parasitic inductance can be reduced by keeping the power
path components close together and keeping the area of the
loops that high currents travel small. Short, thick traces or
copper pours (shapes) are best. In particular, the switch node
(where L1, D1, and the SW pin connect) should be just large
enough to connect all three components without excessive
heating from the current it carries. The LM3402/02HV oper-
ates in two distinct cycles whose high current paths are shown
in Figure 6:
20192128
FIGURE 6. Buck Converter Current Loops
The dark grey, inner loop represents the high current path
during the MOSFET on-time. The light grey, outer loop rep-
resents the high current path during the off-time.
GROUND PLANE AND SHAPE ROUTING
The diagram of Figure 6 is also useful for analyzing the flow
of continuous current vs. the flow of pulsating currents. The
circuit paths with current flow during both the on-time and off-
time are considered to be continuous current, while those that
carry current during the on-time or off-time only are pulsating
currents. Preference in routing should be given to the pulsat-
ing current paths, as these are the portions of the circuit most
likely to emit EMI. The ground plane of a PCB is a conductor
and return path, and it is susceptible to noise injection just as
any other circuit path. The continuous current paths on the
ground net can be routed on the system ground plane with
www.national.com
20
LM3402/LM3402HV
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