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参数资料
| 型号： | LM3431SD |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 1100 kHz SWITCHING FREQ-MAX, QCC28 |
| 封装： | LLP-28 |
| 文件页数： | 7/24页 |
| 文件大小： | 549K |
| 代理商： | LM3431SD |
nation of Rc and Cc is recommended for the compensation
network, shown as R9 and C4 in the typical application circuit.
The series combination of Rc and Cc introduces a pole-zero
pair according to the following equations:
where R
O is the output impedance of the error amplifier, ap-
proximately 500 k
. The initial value of R
C is determined
based on the required crossover frequency from the following
equations using the maximum input voltage:
Where B is the mid-frequency compensation gain (in v/v), R4
is the current limit setting resistor, Acm is the control-output
DC gain, and the gm values are given in the electrical char-
acteristic table. Fcross is the maximum allowable crossover
frequency, based on the calculated values of f
pn and RHPz.
Any Rc value lower than the value calculated above can be
used and will ensure a low enough crossover frequency. Rc
should set the B value typically between 0.01v/v and 0.1v/v
(-20db to -40db). Larger values of R
C will give a higher loop
bandwidth.
However, because the dynamic response of the LM3431 is
enhanced by the FF pin (See Setting FF section) the R
C value
can be set conservatively. The typical range for R
C is between
300ohm and 3 k
. Next, select a value for Cc to set the com-
pensation zero, f
zc, to a frequency greater or equal to the
maximum calculated value of f
p1 (fzc cancels the power pole,
f
p1). Since an fzc value of up to a half decade above fp1 is
acceptable, choose a standard capacitor value smaller than
calculated. Confirm that fpc, the dominant low frequency pole
in the control loop, is less than 100 Hz and below f
p1. The
typical range for C
C is between 10 nF and 100 nF. The com-
pensation zero-pole pair is shown graphically below, along
with the total control loop, which is the sum of the compen-
sation and output-control response. Since the calculated
crossover frequency is an approximation, stability should al-
ways be verified on the bench.
30041143
FIGURE 7. Typical Compensation and Total Loop Bode
Plots
When using an output capacitor with a high ESR value, an-
other pole, f
pc2, may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
C2, shown as C13 in the Figure 1. The pole should be
placed at the same frequency as f
z1. This pole can be calcu-
lated as:
To ensure this equation is valid, and that C
C2 can be used
without negatively impacting the effects of R
C and CC, fpc2
must be at least 10 times greater than f
zc.
LED Current Regulator
SETTING LED CURRENT
LED current is independently regulated in each of 3 strings by
regulating the voltage at the SNS pins. Each SNS pin is con-
nected to a sense resistor, shown in the typical application
schematic as R10 - R13. The sense resistor value is calcu-
lated as follows:
Where I
LED is the current in each LED string, REFIN is the
regulated voltage at the REFIN pin, and INDRV is the NPN
base drive current. If using NFETs, INDRV can be ignored. A
minimum REFIN voltage of 100 mV is required, and 200mV
to 300mV is recommended for most applications. The REFIN
voltage is set with a resistor divider connected to the REF pin,
shown as R7 and R8 in the typical application schematic. The
resistor values are calculated as follows:
The sum of R7 and R8 should be approximately 100k to avoid
excessive loading on the REF pin.
15
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LM3431
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