
10125825
FIGURE 3. Thermal Shutdown Characteristics when only
the First-Stage Thermal-Shutdown Mode is Needed
10125826
FIGURE 4. Thermal Shutdown Characteristics when Both
First-Stage and Second-Stage Thermal-Shutdown Modes
are Needed
In
Figure 3, port 1 is enabled into a short. When this occurs,
the MOSFET switch of port 1 repeatedly opens and closes as
the device temperature rises and falls between 145°C and
135°C. In this example, the device temperature never rises
above 160°C. The second stage thermal shutdown is not
used and port 2 remains operational.
When port 1 is enabled into a short in the example illustrated
in
Figure 4, the device temperature immediately rises above
160°C. A higher ambient temperature or a larger number of
shorted outputs can cause the junction temperature to in-
crease, resulting in the difference in behavior between the
current example and the previous one. When the junction
temperature reaches 160°C, all three ports are disabled (port
3 is not shown in the figure) and all three fault-flag signals are
asserted. Just prior to time index 2.5 ms, the device temper-
ature falls below 135°C, all three ports activate, and all three
fault flags are removed. The short condition remains on port
1, however. For the remainder of the example, the device
temperature cycles between 135°C and 145°C, causing port
1 to repeatedly turn on and off but allowing the un-shorted
ports to function normally.
SOFT START
When a power switch is enabled, high levels of current will
flow instantaneously through the LM3543 to charge the large
capacitance at the output of the port. This is likely to exceed
the over-current threshold of the device, at which point the
LM3543 will enter its current-limit mode. The amount of cur-
rent used to charge the output capacitor is then set by the
current-limit circuitry. The device will exit the current-limit
mode when the current needed to continue to charge the out-
put capacitor is less than the LM3543 current-limit level.
FAULT FLAG
The fault flags are open-drain outputs, each capable of sink-
ing up to a 10 mA load current to typically 100 mV above
ground.
A parasitic diode exists between the flag pins and V
IN pins.
Pulling the flag pins to voltages higher than V
IN will forward
bias this diode and will cause an increase in supply current.
This diode will also clamp the voltage on the flag pins to a
diode drop above V
IN.
The fault flag is active (pulled low) when any of the following
conditions are present: under-voltage, current-limit, or ther-
mal-shutdown.
The LM3543 has an internal delay in reporting fault conditions
that is typically 7 ms in length. In start-up, the delay gives the
device time to charge the output capacitor(s) and exit the cur-
rent-limit mode before a flag signal is set. This delay also
prevents flag signal glitches from occurring when brief
changes in operating conditions momentarily place the
LM3543 into one of its three error conditions. If an error con-
dition still exists after the delay interval has elapsed, the
appropriate fault flag(s) will be asserted (pulled low) until the
error condition is removed. In most applications, the 7 ms in-
ternal flag delay eliminates the need to extend the delay with
an external RC delay network.
Application Information
OUTPUT FILTERING
The schematic in
Figure 1 showed a typical application circuit
for the LM3543. The USB specification requires 120 F at the
output of each hub. A three-port hub with 33 F tantalum ca-
pacitors at each port output meets the specification. These
capacitors provide short-term transient current to drive down-
stream devices when hot-plug events occur. Capacitors with
low equivalent-series-resistance should be used to lower the
inrush current flow through the LM3543 during a hot-plug
event.
The rapid change in currents seen during a hot plug event can
generate electromagnetic interference (EMI). To reduce this
effect, ferrite beads in series between the outputs of the
LM3543 and the downstream USB port are recommended.
Beads should also be placed between the ground node of the
LM3543 and the ground nodes of connected downstream
ports. In order to keep voltage drop across the beads to a
minimum, wire with small DC resistance should be used
through the ferrite beads. A 0.01 F - 0.1 F ceramic capacitor
is recommended on each downstream port directly between
the V
bus and ground pins to further reduce EMI effects.
9
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101258 Version 5 Revision 6
Print Date/Time: 2010/02/04 15:48:33
LM3543