参数资料
型号: LM3686TLX-AAEF/NOPB
厂商: National Semiconductor
文件页数: 18/27页
文件大小: 0K
描述: IC REG BUCK SYNC .9A TRPL 12USMD
标准包装: 3,000
类型: 降压(降压)
输出类型: 固定
输出数: 3
输出电压: 1.2V,1.8V,3V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流/电压模式
频率 - 开关: 3MHz
电流 - 输出: 900mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFBGA
包装: 带卷 (TR)
供应商设备封装: 12-uSMD
其它名称: LM3686TLX-AAEF
SNVS520E – AUGUST 2008 – REVISED MAY 2013
Input Capacitor Selection
C IN_DC-DC
A ceramic input capacitor of 4.7 μF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the V BATT pin of the device. A larger value may be used for improved input voltage filtering. Use X7R
or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603. The minimum input capacitance to ensure good performance is 2.2 μF at 3V dc
bias; 1.5 μF at 5V dc bias including tolerances and over ambient temperature range. The input filter capacitor
supplies current to the PFET switch of the LM3686 DC-DC converter in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current
rating. The input current ripple can be calculated as:
I RMS = I OUTMAX x
V OUT
V BATT
§
x ¨ 1 -
?
V OUT
V BATT
+
2
r
12
·
?
1
r=
(V BATT - V OUT ) x V OUT
L x f x I OUTMAX x V BATT
The worst case is when V BATT = 2 x V OUT
(3)
C IN_LILO
If the LILO is used as post regulation no additional capacitor is needed at V IN_LILO as the output filter capacitor of
the DC-DC converter is close by and therefore sufficient.
In case of independent mode use, a 1.0 μF ceramic capacitor is recommended at V IN_LILO if no other filter
capacitor is present in the V IN_LILO supply path. This capacitor must be located a distance of not more than 1 cm
from the V IN_LILO input pin and returned to QGND.
C IN_LDO
An input capacitor is required for stability. It is recommended to use a 1 μF ceramic capacitor and connected
between the V IN_LDO and QGND.
Output Capacitor
C OUT_DCDC
A ceramic output capacitor of 10 μF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use
Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and
0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested
from them as part of the capacitor selection process.
The minimum output capacitance to ensure good performance is 5.75 μF at 1.8V DC bias including
tolerances and over ambient temperature range. The output filter capacitor smooths out current flow from the
inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform
these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and by the R ESR and
can be calculated as:
Voltage peak-to-peak ripple due to capacitance can be expressed as follow:
V PP-C =
I RIPPLE
4xfxC
(4)
Voltage peak-to-peak ripple due to ESR can be expressed as follow:
V PP-ESR = (2*I RIPPLE ) * R ESR
(5)
18
Product Folder Links: LM3686
Copyright ? 2008–2013, Texas Instruments Incorporated
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