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参数资料
| 型号： | LM4546BVH/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | LM4550 AC '97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound; Package: LQFP; No of Pins: 48; Qty per Container: 250/Tray |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件页数： | 15/27页 |
| 文件大小： | 903K |
| 代理商： | LM4546BVH/NOPB |
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Register Descriptions (Continued)
RECORD GAIN REGISTER (1Ch)
This register controls the input levels for both channels of the
stereo ADC. The inputs come from the Record Select Mux
and are selected via the Record Select Control register, 1Ah.
The gain of each channel can be individually programmed
from 0 dB to +22.5 dB in 1.5 dB steps. Both channels can
also be muted by setting the MSB to 1.
Record Gain Register (1Ch)
Mute
Gx3:Gx0
Function
0
1111
+22.5 dB gain
0
0000
0 dB gain
1
XXXX
*mute
Default: 8000h
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions imple-
mented on the LM4546B. The miscellaneous control bits
include POP which allows the DAC output to bypass the
National 3D Sound circuitry, 3D which enables or disables
the National 3D Sound circuitry, MIX which selects the MO-
NO_OUT source, MS which controls the Microphone Selec-
tion mux, and LPBK which connects the 18 bit output of the
stereo ADC to the 18 bit input of the stereo DAC, bypassing
the Sample Rate Conversion (SRC) logic. LPBK provides a
mixed-mode analog and digital loopback path between ana-
log inputs and analog outputs.
BIT
Function
POP
PCM Out Path:
*0 = 3D allowed
1 = 3D bypassed
3D
National 3D Sound:
*0 = off
1= on
MIX
Mono output select:
*0 = Mix
1 = Mic
MS
Mic select:
*0 = MIC1
1 = MIC2
LPBK
ADC/DAC Loopback:
*0 = No Loopback
1 = Loopback
Default: 0000h
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC ’97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem
readiness and also to program the LM4546B powerdown
states. The 4 LSBs indicate status and 6 of the 8 MSBs
control powerdown.
The 4 LSBs of this register indicate the status of the 4 audio
subsections of the codec: Reference voltage, Analog mixers
and amplifiers, DAC section, ADC section. When the "Codec
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97
registers are in a fully operational state and that control and
status information can be transferred. It does NOT indicate
that the codec is ready to send or receive audio PCM data or
to pass signals through the analog I/O and mixers. To deter-
mine that readiness, the Controller must check that the 4
LSBs of this register are set to “1” indicating that the appro-
priate audio subsections are ready.
The powerdown bits PR0 – PR5 control internal subsections
of the codec. They are implemented in compliance with AC
’97 Rev 2.1 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
REF in addition to all the same mixer circuits as PR2. PR4
powers down the AC Link digital interface – see Figure 8 for
signal powerdown timing. PR5 disables internal clocks. PR6
and PR7 are not used.
BIT#
BIT
Function: Status
0
ADC
1 = ADC section ready to
transmit data
1
DAC
1 = DAC section ready to
accept data
2
ANL
1 = Analog mixers ready
3
REF
1 = V
REF is up to nominal level
BIT#
BIT
Function: Powerdown
8
PR0
1 = Powerdown ADCs and
Record Select Mux
9
PR1
1 = Powerdown DACs
10
PR2
1 = Powerdown Analog Mixer
(V
REF still on)
11
PR3
1 = Powerdown Analog Mixer
(V
REF off)
12
PR4
1 = Powerdown AC Link digital
interface (BIT_CLK off)
13
PR5
1 = Disable Internal Clock
14
PR6
Not Used
15
PR7
Not Used
Default: 000Fh If ready; otherwise 000Xh (see text)
EXTENDED AUDIO ID REGISTER (28h)
This read-only register (X001h) identifies which AC ’97 Ex-
tended Audio features are supported. The LM4546B features
VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec
support). VRA is indicated by a "1" in bit 0. The two MSBs,
ID1 and ID0, show the current Codec Identity as defined by
the Identity pins ID1#, ID0# (pins 46 and 45). Note that the
external logic connections to ID1#, ID0#, are inverse in
polarity to the value of the Codec Identity (ID1, ID0) held in
bits D15, D14. Codec mode selections are shown in the
table below.
Pin 46
(ID1)
Pin 45
(ID0)
D15,28h
(ID1)
D14,28h
(ID0)
Codec Identity
Mode
NC/DV
DD
NC/DV
DD
0
Primary
NC/DV
DD
GND
0
1
Secondary 1
LM4546B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM4546BVHX | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| LM4546BVHX/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| LM4546VH | 制造商:Texas Instruments 功能描述:SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| LM4547VH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Soundcard Circuits |
| LM4548 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound |
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