参数资料
型号: LM4681SQ
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 音频/视频放大
英文描述: 10 Watt Stereo CLASS D Audio Power Amplifier with Stereo Headphone Amplifier and I2C/SPI Volume Control
中文描述: 10 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC48
封装: LLP-48
文件页数: 7/19页
文件大小: 983K
代理商: LM4681SQ
General Features (Continued)
I
2C Timing Diagrams
SPI Timing Diagram
SPI Operational Requirements
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (t
CH ) after
the rising edge of CLK, and CLK must remain logic-low for at
least 100ns (t
CL ) after the falling edge of CLK.
3. Data bits are written to the DATA pin with the most
significant bit (MSB) first.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 50ns (t
DS) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 50ns (t
DH) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
5. ENABLE should be logic-low only during serial data trans-
mission.
6. ENABLE must be logic-low at least 50ns (t
ES ) before the
first rising edge of CLK, and ENABLE has to remain logic-
low at least 50ns (t
EH ) after the eighth rising edge of CLK.
7. If ENABLE remains logic-high for more than 50ns before
all 8 bits are transmitted then the data latch will be aborted.
20118919
FIGURE 1. I
2C Bus Format
20118920
FIGURE 2. I
2C Timing Diagram
20118921
FIGURE 3.
LM4681
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