参数资料
型号: LM5041BSDX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 685 kHz SWITCHING FREQ-MAX, DSO16
封装: 5 X 5 MM, LLP-16
文件页数: 12/16页
文件大小: 426K
代理商: LM5041BSDX
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Oscillator
Frequency1
RT = 26.7 k
180
175
200
220
225
kHz
Frequency2
RT = 7.87 k
515
600
685
kHz
Sync threshold
-
3
3.5
V
PWM Comparator
Delay to Output
COMP = 2V, CS stepped 0 to 0.4V
Time to onset of OUT transition low
-
25
-
ns
Max Duty Cycle
TS = Oscillator Period
-
(Ts-240ns)
/ Ts
-
%
Min Duty Cycle
COMP = 0V
-
0
%
COMP to PWM Comparator Gain
-
0.32
-
COMP Open Circuit Voltage
FB = 0V
4.1
4.8
5.5
V
COMP Short Circuit Current
FB = 0V, COMP = 0V
0.6
1
1.4
mA
Slope Compensation
Slope Comp Amplitude
Delta increase at PWM Comparator
to CS
-
110
-
mV
UVLO Shutdown
Under-Voltage Shutdown
2.44
2.5
2.56
V
Under-voltage Shutdown
Hysteresis Current Source
16
20
24
A
Buck Stage Outputs
Output High level
-
5 (V
REF)
-
V
Output High Saturation
I
OUT = 10 mA, REF = VOUT
-
0.5
1
V
Output Low Saturation
I
OUT = 10 mA
-
0.5
1
V
Rise Time
C
L = 100 pF
-
10
-
ns
Fall Time
C
L = 100 pF
-
10
-
ns
Push-Pull Outputs
Overlap Time
R
SET = 20 k Connected to GND,
50% to 50% Transitions
60
90
120
ns
Dead Time
R
SET = 20k Connected to REF,
50% to 50% Transitions
65
95
125
ns
Output High Saturation
I
OUT = 50 mA
V
CC - VOUT
-
0.25
0.5
V
Output Low Saturation
I
OUT = 100 mA
-
0.5
1
V
Rise Time
C
L = 1 nF
-
20
ns
Fall Time
C
L = 1 nF
-
20
-
ns
Thermal Shutdown
T
SD
Thermal Shutdown Temp.
-
165
-
°C
Thermal Shutdown Hysteresis
-
25
-
°C
Thermal Resistance
θ
JA
Thermal Resistance
Junction to Ambient
TSSOP Package
-
125
-
°C/W
LLP Package
-
32
-
°C/W
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin. Test Method is per JESD-22-A114.
Note 3:
For detailed information on soldering plastic TSSOP and LLP packages, please refer to Application Note AN-1520: A Guide to Board Layout for Best
Thermal Resistance for Exposed Packages , Application Note AN-1187: Leadless Leadframe Package (LLP) , or go to www.national.com/packaging for more
information.
Note 4:
Device thermal limitations may limit usable range.
5
www.national.com
LM5041B
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