参数资料
型号: LM75AD/G-T
厂商: NXP Semiconductors
文件页数: 5/24页
文件大小: 137K
描述: IC I2C TEMP SNSR/WATCHDOG 8-SOIC
标准包装: 1
功能: 温度监视系统(传感器),监视器
传感器类型: 内部
感应温度: -55°C ~ 125°C
精确度: ±3°C(最小值)
拓扑: ADC(三角积分型),比较器,振荡器,寄存器库
输出类型: 2 线串行,I²C?
输出警报:
输出风扇:
电源电压: 2.8 V ~ 5.5 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 剪切带 (CT)
配用: 568-4002-ND - DEMO BOARD I2C
其它名称: 568-1889-1
LM75A_4
?NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04  10 July 2007
5 of 24
NXP Semiconductors
LM75A
Digital temperature sensor and thermal watchdog
In both cases, comparator mode and interrupt mode, the OS output is activated only if a
number of consecutive faults, dened by the device fault queue, has been met. The fault
queue is programmable and stored in the two bits, B3 and B4, of the Conguration
register. Also, the OS output active state is selectable as HIGH or LOW by setting
accordingly the conguration register bit B2.
At power-up, the device is put into normal operation mode, the T
os
is set to 80 癈, the T
hyst
is set to 75 癈, the OS active state is selected LOW and the fault queue is equal to 1. The
temp reading data is not available until the rst conversion is completed in about 100 ms.
The OS response to the temperature is illustrated in
Figure
4.
7.2  I
2
C-bus serial interface
The LM75A can be connected to a compatible 2-wire serial interface I
2
C-bus as a slave
device under the control of a controller or master device, using two device terminals, SCL
and SDA. The controller must provide the SCL clock signal and write/read data to/from the
device through the SDA terminal. Notice that if the I
2
C-bus common pull-up resistors have
not been installed as required for I
2
C-bus, then an external pull-up resistor, about 10 k&,
is needed for each of these two terminals. The bus communication protocols are
described in
Section
7.10.
7.3  Slave address
The LM75A slave address on the I
2
C-bus is partially dened by the logic applied to the
device address pins A2, A1 and A0. Each of them is typically connected either to GND for
logic 0, or to V
CC
 for logic 1. These pins represent the three LSB bits of the device 7-bit
address. The other four MSB bits of the address data are preset to 1001 by hard wiring
inside the LM75A.
T
ab
le
4 shows the devices complete address and indicates that up to
(1)  OS is reset by either reading register. It is assumed that the fault queue is met at each T
os
and
T
hyst
 crossing point.
Fig 4.   OS response to temperature
002aad032
(1)
(1)
(1)
T
os
T
hyst
OS reset
OS active
OS reset
OS active
OS output in comparator mode
OS output in interrupt mode
reading temperature limits
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