参数资料
型号: LM96194CIAQX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 电源管理
英文描述: 9-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48
封装: LLP-48
文件页数: 14/24页
文件大小: 542K
代理商: LM96194CIAQX
Symbol
Pin #
Circuit
All Input Circuits
AD_IN4
30
E
Circuit D
AD_IN5
31
E
GND
32
E
GND
33
E
GND
34
E
AD_IN6
35
E
AD_IN7
36
E
AD_IN8
37
D
ADDR_SEL
38
A
AD_IN9/V
DD (V+)
39
B
Circuit E
GND
40
B (Internally
shorted to AGND.)
PWM1
41
A
PWM2
42
A
P1_VID0
43
A
P1_VID1
44
A
P1_VID2
45
A
P1_VID3
46
A
P1_VID4
47
A
P1_VID5
48
A
Note 4:
Human body model, 100 pF discharged through a 1.5 k
resistor. Machine model, 200 pF discharged directly into each pin. Charged device model (CDM)
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 5:
Reflow temperature profiles are different for lead-free and non lead-free packages.
Note 6:
The maximum power dissipation must be de-rated at elevated temperatures and is dictated by T
JMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D MAX= (TJMAX TA) / θJA. The θJAfor the LM96194 when mounted to 1 oz. copper foil PCB the θJA with different
air flow is listed in the following table.
Air Flow
Junction to Ambient Thermal Resistance,
θ
JA
0 m/s
28 °C/W
1.14 m/s (225 LFPM)
25 °C/W
2.54 m/s (500 LFPM)
22 °C/W
Note 7:
See the URL "http://www.national.com/packaging/" for other recommendations and methods of soldering surface mount devices.
Note 8:
At the time of first pubication of this specification (Jan 2006), this specification applies to either Pentium or Xeon Processors on 90nm or 65nm process
when TruTherm is selected. When TruTherm is deselected this specification applies to an MMBT3904. This specification does include the error caused by the
variability of the diode ideality and series resistance parameters.
Note 9:
Typical parameters are at T
J = TA = 25 °C and represent most likely parametric norm.
Note 10:
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 12:
Total Monitoring Cycle Time includes all temperature and voltage conversions.
Note 13:
Leakage current approximately doubles every 20 °C.
Note 14:
A total digital I/O current of 40 mA can cause 6 mV of offset in Vref.
Note 15:
Timing specifications are tested at the TTL logic levels, V
IL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
21
www.national.com
LM96194
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