参数资料
型号: LMK04031BISQ/NOPB
厂商: National Semiconductor
文件页数: 40/65页
文件大小: 0K
描述: IC CLOCK CONDITIONER W/PLL 48LLP
标准包装: 1,000
系列: PowerWise®
类型: 时钟调节器
PLL:
输入: LVCMOS
输出: LVCMOS,LVDS,2VPECL,LVPECL
电路数: 1
比率 - 输入:输出: 2:6
差分 - 输入:输出: 是/是
频率 - 最大: 1.57GHz
除法器/乘法器: 是/是
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-LLP(7x7)
包装: 带卷 (TR)
其它名称: LMK04031BISQ
C2
PLL2
Phase
Detector
R2
C1
C3
C4
R3
R4
LMK040xx
PLL2 Internal Loop Filter
PLL2 External Loop
Filter
C2
PLL1
Phase
Detector
R2
CPout1
C1
LMK040xx
PLL1 External Loop
Filter
C
Po
u
t2
External VCXO
Internal VCO
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Figure 14. Loop Filter
Table 33. Typical Current Consumption for Selected Functional Blocks
Power
Typical ICC
Power
Dissipated in
(Temp = 25 °C,
Dissipated in
LVPECL/2VPECL
Block
Condition
VCC = 3.3 V)
device
Emitter
(mA)
(mW)
Resistors
(mW)
Single input clock (CLKIN_SEL = 0 or 1); LOS disabled;
Entire device,
PLL1 and PLL2 locked; All CLKouts are off; No LVPECL
115
380
-
core current
emitter resistors connected
REFMUX
Enable auto-switch mode (CLKIN_SEL = 2 or 3)
4.3
14
-
LOS
Enable LOS (LOS_TYPE = 1, or 2, or 3)
3.6
12
-
Low Channel
The low channel internal buffer is enabled when CLKout0 is
10
33
-
Internal Buffer
enabled
High Channel
The high channel internal buffer is enabled when one of
10
33
-
Internal Buffer
CLKout1 through CLKout4 is enabled
Divider bypassed (CLKout_MUX = 0, 2)
0
-
Divide circuitry
Divider enabled, divide = 2 (CLKout_MUX = 1, 3)
5.3
17
-
per output
Divider enabled, divide > 2 (CLKout_MUX = 1, 3)
8.5
28
-
Delay bypassed (CLKout_MUX = 0, 1)
0
-
Delay circuitry per
Delay enabled, delay < 8 (CLKout_MUX = 2, 3)
5.8
19
-
output
Delay enabled, delay > 7 (CLKout_MUX = 2, 3)
9.9
33
-
Fout Buffer
EN_Fout = 1
14.5
48
-
LVDS Buffer
LVDS buffer, enabled
19.3
64
-
Copyright 2008–2011, Texas Instruments Incorporated
45
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